eds1232aase Elpida Memory, Inc., eds1232aase Datasheet - Page 35

• Manufacturer Part Number: eds1232aase
• Description: 128m Bits Sdram
• Manufacturer: Elpida Memory, Inc.

Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1
Data Sheet E0350E31 (Ver. 3.1)
bank as the preceding write command, the read command can be performed after an interval of no less than 1
clock. However, in the case of a burst write, data will continue to be written until one clock before the read
command is executed.
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will
continue to be written until one clock before the read command is executed (as in the case of the same bank and
the same address).
DQ (output)
DQ (output)
Command
Command
DQ (input)
DQ (input)
DQM
DQM
CLK
CLK
Column = A
Write
WRIT
in A0
Column = A
Write
WRIT
in A0
WRITE to READ Command Interval (1)
WRITE to READ Command Interval (2)
in A1
Column = B
Read
READ
Column = B
Read
READ
35
Column = B
Dout
out B0
/CAS Latency
Column = B
Dout
out B0
/CAS Latency
out B1
out B1
out B2
out B2
out B3
EDS1232AASE
out B3
Burst Write Mode
Burst Write Mode
Bank 0
CL = 2
BL = 4
Bank 0
CL = 2
BL = 4