eds1232aase Elpida Memory, Inc., eds1232aase Datasheet - Page 34

• Manufacturer Part Number: eds1232aase
• Description: 128m Bits Sdram
• Manufacturer: Elpida Memory, Inc.

Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1
Data Sheet E0350E31 (Ver. 3.1)
bank as the preceding read command, the write command can be performed after an interval of no less than 1
clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the
output buffer becomes High-Z before data input.
DQM
DQ (output)
Command
DQ (input)
DQ
Command
CL=2
CL=3
CLK
CL=2
CL=3
DQM
CLK
READ to WRITE Command Interval (1)
READ to WRITE Command Interval (2)
READ
READ WRIT
High-Z
in B0
out
in B1
34
out
out
in B2
2 clock
out
out
in B3
WRIT
in
in
in
in
in
in
EDS1232AASE
BL = 4
Burst write
in
in