eds1232aase Elpida Memory, Inc., eds1232aase Datasheet - Page 13

• Manufacturer Part Number: eds1232aase
• Description: 128m Bits Sdram
• Manufacturer: Elpida Memory, Inc.

Read command (/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met. This command sets the burst start address
given by the column address.
CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle
(precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or
activate command), the Synchronous DRAM cannot accept any other command
Data Sheet E0350E31 (Ver. 3.1)
Column Address and and Read Command
CBR (auto) Refresh Command
(Bank select)
(Bank select)
BA0, BA1
BA0, BA1
/RAS
/CAS
/RAS
/CAS
CKE
CKE
CLK
CLK
/WE
/WE
A10
Add
A10
Add
/CS
/CS
13
H
H
Col.
EDS1232AASE