eds1232aase Elpida Memory, Inc., eds1232aase Datasheet - Page 11

• Manufacturer Part Number: eds1232aase
• Description: 128m Bits Sdram
• Manufacturer: Elpida Memory, Inc.

Command Operation
Mode register set command (/CS, /RAS, /CAS, /WE)
The Synchronous DRAM has a mode register that defines how the device operates. In this command, A0 through
A11 are the data input pins. After power on, the mode register set command must be executed to initialize the
device. The mode register can be set only when all banks are in idle state. During 2CLK (tRSC) following this
command, the Synchronous DRAM cannot accept any other commands.
Activate command (/CS, /RAS = Low, /CAS, /WE = High)
The Synchronous DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0
and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's
/RAS falling.
Data Sheet E0350E31 (Ver. 3.1)
Row Address Strobe and Bank Activate Command
Mode Register Set Command
(Bank select)
BA0, BA1
(Bank select)
BA0, BA1
/RAS
/CAS
/RAS
/CAS
CKE
CKE
CLK
/WE
CLK
/WE
A10
Add
/CS
A10
Add
/CS
11
H
H
Row
Row
EDS1232AASE