UPD16449N NEC [NEC], UPD16449N Datasheet
UPD16449N
Related parts for UPD16449N
UPD16449N Summary of contents
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SOURCE DRIVER FOR 240-OUTPUT TFT-LCD (NAVIGATION, AUTOMOBILE LCD-TV) DESCRIPTION PD16449 is a source driver for TFT liquid crystal panels. This IC consists of a multiplexer circuit supporting a variety of pixel arrays, a shift register that generates sampling timing, and ...
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BLOCK DIAGRAM STHR R,/L CLI1 to CLI3 INH C 1 RESET C1 C2 Multiplexer C3 MP/TH MP/1 SAMPLE AND HOLD CIRCUIT AND OUTPUT CIRCUIT Swa1 Video Line Swa2 2 240-bit bidirectional shift register ...
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PIN CONFIGURATION DD2 V DD2 V DD2 V DD1 V DD1 V DD1 STHL STHL STHL MP/TH MP/TH MP/TH MP/1.5 MP/1.5 MP/1.5 R,/L R,/L R,/L RESET RESET RESET INH ...
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No. PAD Name -400 2 C1 -400 3 C1 -400 4 C2 -400 5 C2 -400 6 C2 -400 7 C3 -400 8 C3 -400 9 C3 -400 10 VDD2 -400 11 VDD2 -400 12 ...
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No. PAD Name 111 H47 327 112 H48 327 113 H49 327 114 H50 327 115 H51 327 116 H52 327 117 H53 327 118 H54 327 119 H55 327 120 H56 327 121 H57 327 122 ...
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No. PAD Name 221 H157 327 222 H158 327 223 H159 327 224 H160 327 225 H161 327 226 H162 327 227 H163 327 228 H164 327 229 H165 327 230 H166 327 231 H167 327 232 ...
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PIN FUNCTIONS Symbol Pin Name Pad No Video signal input Video signal output 65 to 304 1 300 STHR, Cascade I/O 46, 47 STHL ...
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FUNCTIONAL DISCRIPTION 5.1 Multiplexer Circuit This circuit selects RGB video signals input to the pins according to the pixel array of the liquid crystal panel, and outputs the signals to the H 1 Vertical stripe array, ...
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Figure 5 2. Timing Chart of Vertical Stripe Array RESET INH 240 Sampling C1 (C3) undifined input data Output undifined 239 C2 (C2) Sampling undifined input data Output undifined ...
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Single-side delta array mode (MP/ MP/1 Table 5 2. Relation between Video Signals C1 to C3, and Output Pins Line No. RESET INH (number of INHn ...
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Figure 5 4. Timing Chart of Single-Side Delta Array RESET INH 240 Sampling undifined undifined input data Output undifined 239 undifined Sampling undifined input data Output undifined 238 ...
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Double-side delta array mode (MP/ MP/1 Because the pad pitch of the PD16449 is designed so that the IC is mounted on one side, the output pitch must be expanded on the TCP if the ...
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Figure 5 6. Timing Chart of Both-Sides Delta Array RESET INH 240 Sampling undifined undifined input data Output undifined 239 Sampling undifined undifined input data Output undifined 238 ...
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Mosaic array mode (MP/ MP/1 Table 5 4. Relation between Video Signals C1 to C3, and Output Pins Line No. RESET INH (number of INHn ...
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Figure 5 8. Timing Chart of Mosaic Array RESET INH 240 Sampling undifined undifined input data Output undifined 239 Sampling undifined undifined input data Output undifined 238 undifined ...
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Relation between Shift Clock CLIn and Internal Sampling Pulse SHPn (1) Simultaneous sampling ( ( ) indicates the case of left shift.) CLI1 STHR (STHL) SHP (SHP ) 1 240 SHP (SHP ) 2 239 SHP (SHP ) 3 ...
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Sample and Hold Circuit The sample and hold circuit samples and holds the video input signals C1 through C3 selected by the multiplexer circuit in the timing shown below. Swa1 through Swb2 are reset by the RESET signal and ...
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Cautions 1. Turn on power logic input, V DD1 destruction due to latch-up, and turn off power in the reverse sequence. Observe this power sequence even during the transition period. 2. The PD16449 is designed to input ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Logic supply voltage V DD1 Driver supply voltage V DD2 Logic input voltage V I Video input voltage V VI Logic output voltage V 01 Driver ...
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Electrical Characteristics ( + Parameter Maximum video signal output voltage V Minimum video signal output voltage V Logic high level output voltage V Logic low level output voltage V Video signal high level output ...
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Switching Characteristics ( + Parameter Symbol Start pulse propagation delay t PHL time t PLH Clock frequency 1 f CLK 1 Clock frequency 2 f CLK 2 Logic input capacitance C I1 STHL, STHR ...
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Switching Characteristic Waveform (Simultaneous/successive sampling) Start Pulse Input Timing PW 1 CLI 50% CLI1 t SETUP STHR 50% (STHL) SHP 1 (SHP ) 240 Start Pulse Output Timing 50% CLI1 t PLH STHL (STHR) Remark The input/output timing of the ...
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RESET INH Pulse Timing CLI1 PW RES 50% RESET INH 50% 50 IIHOLD ISETUP 50 INH R-I Data Sheet S15677EJ1V0DS PD16449 50% 23 ...
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Data Sheet S15677EJ1V0DS PD16449 ...
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Data Sheet S15677EJ1V0DS PD16449 25 ...
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Data Sheet S15677EJ1V0DS PD16449 ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...