lxt972a Intel Corporation, lxt972a Datasheet - Page 31

• Manufacturer Part Number: lxt972a
• Description: 3.3v Dual-speed Fast Ethernet Transceiver Datasheet
• Manufacturer: Intel Corporation

3.7.2
3.7.3
3.7.3.1
Datasheet
TXD<3:0>
TXD<3:0>
TX_CLK
TX_EN
TX_CLK
Figure 17. 100BASE-TX Transmission with no Errors
Figure 18. 100BASE-TX Transmission with Collision
TX_EN
CRS
COL
CRS
COL
Collision Indication
Figure 17
and remains asserted for the duration of the collision as shown in
100BASE-X Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT972A is a Physical Layer 1 (PHY)
device. The LXT972A implements the Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model
defined by the IEEE 802.3u standard. The following paragraphs discuss LXT972A operation from
the reference model point of view.
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/
decoding function.
For 100TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long
as TX_EN is de-asserted.
P
P
R
R
shows normal transmission. Upon detection of a collision, the COL output is asserted
E
E
A
A
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A
M
M
B
B
L
L
E
E
DA
JAM
DA DA DA DA
JAM
JAM
Figure
DA
DA
18.
JAM
DA
DA
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