lxt972a Intel Corporation, lxt972a Datasheet
lxt972a
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lxt972a Summary of contents
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... This document also supports the LXT972. The LXT972A supports full-duplex operation at 10Mbps and 100Mbps. Its operating condition can be set using auto-negotiation, parallel detection, or manual control. The LXT972A is fabricated with an advanced CMOS process and requires only a single 3.3V power supply. Applications Combination 10BASE-T/100BASE-TX ...
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... Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT972A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... Establishing Link .................................................................................................24 3.5.1 Auto-Negotiation.....................................................................................24 3.5.1.1 Base Page Exchange................................................................24 3.5.1.2 Next Page Exchange.................................................................24 3.5.1.3 Controlling Auto-Negotiation .....................................................25 3.5.2 Parallel Detection ...................................................................................25 3.6 MII Operation.......................................................................................................25 3.6.1 MII Clocks...............................................................................................26 3.6.2 Transmit Enable .....................................................................................26 3.6.3 Receive Data Valid.................................................................................26 3.6.4 Carrier Sense .........................................................................................26 3.6.5 Error Signals...........................................................................................26 3.6.6 Collision..................................................................................................26 3.6.7 Loopback................................................................................................28 3.6.7.1 Operational Loopback ...............................................................28 3.6.7.2 Test Loopback ...........................................................................28 3.7 100Mbps Operation.............................................................................................29 Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A 3 ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 3.7.1 100BASE-X Network Operations ........................................................... 29 3.7.2 Collision Indication ................................................................................. 31 3.7.3 100BASE-X Protocol Sublayer Operations ............................................ 31 3.7.3.1 PCS Sublayer............................................................................ 31 3.7.3.2 PMA Sublayer ........................................................................... 34 3.7.3.3 Twisted-Pair PMD Sublayer ...................................................... 34 3.8 10Mbps Operation............................................................................................... 35 3.8.1 10T Preamble Handling ......................................................................... 35 3.8.2 10T Carrier Sense.................................................................................. 36 3.8.3 10T Dribble Bits...................................................................................... 36 3.8.4 10T Link Integrity Test............................................................................ 36 3.8.4.1 Link Failure................................................................................ 36 3.8.5 10T SQE (Heartbeat) ............................................................................. 36 3 ...
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... LXT972A MII Signal Descriptions........................................................................13 3 LXT972A Network Interface Signal Descriptions ................................................14 4 LXT972A Miscellaneous Signal Descriptions......................................................14 5 LXT972A Power Supply Signal Descriptions ......................................................15 6 LXT972A JTAG Test Signal Descriptions ...........................................................15 7 LXT972A LED Signal Descriptions......................................................................15 8 Hardware Configuration Settings ........................................................................24 Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A 5 ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 9 Carrier Sense, Loopback, and Collision Conditions............................................ 28 10 4B/5B Coding ...................................................................................................... 33 11 BSR Mode of Operation ...................................................................................... 39 12 Supported JTAG Instructions .............................................................................. 39 13 Device ID Register .............................................................................................. 39 14 Magnetics Requirements .................................................................................... 40 15 RJ-45 Pin Comparison of NIC and Switch Twisted-Pair Interfaces .................... 40 16 Absolute Maximum Ratings ................................................................................ 44 17 Operating Conditions ...
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... Revision Date 002 January 2001 Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A Clock Requirements: Modified language under Clock Requirements heading. I/O Characteristics REFCLK (table): Changed values for Input Clock Duty Cycle under Min from and under Max from 60 to 65. Description ...
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... LED/CFG<3:1> Collision COL Detect RX_CLK RXD<3:0> Serial-to- Parallel RXDV Converter Carrier Sense CRS Data Valid Error Detect RX_ER Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A Clock Generator Manchester 10 OSP Encoder ™ Pulse Scrambler 100 Shaper & Encoder Auto Negotiation OSP ...
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... GND 14 GND 15 GND 16 Package Topside Markings Marking Part # LXT972A is the unique identifier for this product family. Identifies the particular silicon “stepping” (Refer to Specification Update for additional stepping Rev # information.) Lot # Identifies the batch. FPO # Identifies the Finish Process Order. 10 Part # ...
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... TCK 31 TRST 32 GND 33 PAUSE 34 TEST0 35 TEST1 36 LED/CFG3 Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A Reference for Type Full Description Input Table 4 on page 14 Output Table 4 on page 14 Input Table 2 on page 13 Input Table 4 on page 14 Input Table 4 on page 14 Input Table 4 on page 14 – ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet Table 1. LQFP Numeric Pin List (Continued) Pin Symbol 37 LED/CFG2 38 LED/CFG1 39 PWRDWN 40 VCCIO 41 GND 42 MDIO 43 MDC 44 N/C 45 RXD3 46 RXD2 47 RXD1 48 RXD0 49 RX_DV 50 GND 51 VCCD 52 RX_CLK 53 RX_ER 54 TX_ER 55 TX_CLK 56 TX_EN 57 TXD0 58 TXD1 59 TXD2 60 TXD3 61 GND 62 COL ...
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... Receive Data. RXD is a bundle of parallel signals that transition synchronously with O respect to the RX_CLK. RXD<0> is the least significant bit. 47 RXD1 48 RXD0 Receive Data Valid. The LXT972A asserts this signal when it drives valid data on RXD. 49 RX_DV O This output is synchronous to RX_CLK. Receive Error. Signals a receive error condition has occurred. This output is synchronous 53 ...
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... Test. Tie Low. Test. Tie Low. Power Down. When set High, this pin puts the LXT972A in a power-down mode. Crystal Input and Output MHz crystal oscillator circuit can be connected across XI and XO. A clock can also be used at XI. Refer to Functional Description for detailed clock requirements ...
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... I/O 36 LED/CFG3 1. Type Column Coding Input Output Analog Open Drain Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A Signal Description Digital Power. Requires a 3.3V power supply. Ground. MII Power. Requires either a 3. 2.5V supply. Must be supplied from the same source used to power the MAC on the other side of the MII. ...
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... If the PHY device on the other side of the link supports auto- negotiation, the LXT972A auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT972A automatically detects the presence of either link pulses (10Mbps PHY) or Idle symbols (100Mbps PHY) and set its operating conditions accordingly ...
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... Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete this interface. On the transmit side, the LXT972A has an active internal termination and does not require external termination resistors. Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to page 14) allow the designer to match the output waveform to the magnetic characteristics ...
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... The LXT972A supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT972A. The MDIO interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers ...
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... Link status change 3.2.3.3 Hardware Control Interface The LXT972A provides a Hardware Control Interface for applications where the MDIO is not desired. The Hardware Control Interface uses the three LED driver pins to set device configuration. Refer to Section 3.4.5, “Hardware Configuration Settings” on page 23 Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — ...
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... Clock Requirements 3.3.2.1 External Crystal/Oscillator The LXT972A requires a reference clock input that is used to generate transmit signals and recover receive signals. It may be provided by either of two methods: by connecting a crystal across the oscillator pins (XI and XO connecting an external clock source to pin XI. The connection of a clock source to the XI pin requires the XO pin to be left open. A crystal-based clock is recommended over a derived clock (i ...
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... Initialization When the LXT972A is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control or MDIO interface as shown in Figure 6 ...
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... Hardware Power Down The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the following conditions are true: • The LXT972A network port and clock are shut down. • All outputs are tri-stated. • All weak pad pull-up and pull-down resistors are disabled. ...
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... Hardware Configuration Settings The LXT972A provides a hardware option to set the initial device configuration. The hardware option uses the three LED driver pins. This provides three control bits, as listed in LED drivers can operate as either open-drain or open-source circuits as shown in ...
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... Each FLP burst exchanges 16 bits of data, which are referred “link code word”. All devices that support auto-negotiation must implement the “Base Page” defined by IEEE 802.3 (registers 4 and 5). LXT972A also supports the optional “Next Page” function as described in 3 ...
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... Separate channels are provided for transmitting data from the MAC to the LXT972A (TXD), and for passing data received from the line (RXD) to the MAC. Each channel has its own clock, data bus, and control signals. Nine signals are used to pass received data to the MAC: RXD< ...
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... Error Signals When LXT972A is in 100Mbps mode and receives an invalid symbol from the network, it asserts RX_ER and drives “1110” on the RXD pins. When the MAC asserts TX_ER, the LXT972A drives “H” symbols out on the TPOP/N pins. ...
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... XI Figure 11. Link Down Clock Transition RX_CLK TX_CLK Any Clock Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A Constant 25 MHz Constant 25 MHz Link Down condition/Auto Negotiate Enabled 2.5MHz Clock Clock transition time will not exceed 2X the nominal clock period: (10Mbps = 2.5 MHz; 100Mbps = 25 MHz) ...
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... Test Loopback A test loopback function is provided for diagnostic testing of the LXT972A. During test loopback, the twisted-pair interface is disabled. Data transmitted by the MAC is internally looped back by the LXT972A and returned to the MAC. Test loopback is available for both 100TX and 10T operation. Test loopback is enabled by setting bits as follows: • ...
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... During 100BASE-X operation, the LXT972A transmits and receives 5-bit symbols across the network link. Figure 13 actively transmitting data, the LXT972A sends out Idle symbols on the line. In 100TX mode, the LXT972A scrambles and transmits the data to the network using MLT-3 line code (Figure 14 on page and sent across the MII to the MAC. ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet As shown in Figure 13 on page soon as the LXT972A detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD, symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the balance of the preamble, the SFD, packet data, and CRC. ...
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... COL 3.7.3 100BASE-X Protocol Sublayer Operations With respect to the 7-layer communications model, the LXT972A is a Physical Layer 1 (PHY) device. The LXT972A implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802.3u standard. The following paragraphs discuss LXT972A operation from the reference model point of view ...
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... SSD. Dribble Bits The LXT972A handles dribbles bits in all modes. If between one through four dribble bits are received, the nibble is passed across the MII, padded with 1s if necessary. If between five through seven dribble bits are received, the second nibble is not sent onto the MII bus. ...
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... The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. 3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T /H/ (Error) code group is used to signal an error condition. Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A 5B Code ...
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... LXT972A to re-negotiate. Link Failure Override The LXT972A normally transmits data packets only if it detects the link is up. Setting bit 16. overrides this function, allowing the LXT972A to transmit data packets even when the link is down. This feature is provided as a diagnostic tool. Note that auto-negotiation must be disabled to transmit data packets in the absence of link ...
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... LXT972A strips the entire preamble off of received packets. CRS is asserted coincident with SFD. RX_DV is held Low for the duration of the preamble. When RX_DV is asserted, the very first two nibbles driven by the LXT972A are the SFD “5D” hex followed by the body of the packet. ...
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... Register, the LXT972A transmits packets, regardless of link status. 3.8.5 10T SQE (Heartbeat) By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT972A. To enable this function, set bit 16 When this function is enabled, the LXT972A asserts its COL output for 5-15 BT after each packet. See 3.8.6 10T Jabber If a transmission exceeds the jabber timer, the LXT972A disables the transmit and loopback functions ...
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... Bits 6.1 and 6.5 are cleared when read. 3.9.2 LED Functions The LXT972A incorporates three direct LED drivers. On power up all the drivers are asserted for approximately 1 second after reset de-asserts. Each LED driver can be programmed using the LED Configuration Register (refer to • ...
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... Boundary Scan (JTAG1149.1) Functions LXT972A includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. The BSDL file is available by contacting your local sales office (see the back page accessing the Intel web site (developer.intel.com/design/ network/) ...
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... Version Part ID (hex) 0001 03CB 1. The JEDEC 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC (1111 1110) which becomes 111 1110 Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A Table 12. Description Capture Shift Update System Function ...
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... Application Information 4.1 Magnetics Information The LXT972A requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated at 2kV to protect the circuitry from static voltages across the connectors and cables. Refer to A cross-reference list of magnetic manufacturers and part numbers is available in Application Note 073, Magnetic Manufacturers, which can be found on the Intel web site (developer ...
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... A separate ferrite bead (rated at 50 mA) should be used to supply center tap current. 2. The 100 transmit load termination resistor typically required is integrated in the LXT972A. 3. Magnetics without a receive pair center tap do not require termination. 4. RJ-45 connections shown are for a standard switch application. For a standard NIC RJ-45 setup, see Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — ...
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... A separate ferrite bead (rated at 50 mA) should be used to supply center tap current. 2. The 100 transmit load termination resistor typically required is integrated in the LXT972A. 3. Magnetics without a receive pair center tap do not require a 2kV termination. 4. RJ-45 connections shown are for a standard NIC. Tx/Rx crossover may be required for repeater & switch applications. ...
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... Figure 23. Typical MII Interface TX_EN TX_ER TXD<3:0> TX_CLK RX_CLK MAC RX_DV RX_ER RXD<3:0> CRS COL Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A LXT972A X F RJ- ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 5.0 Test Specifications Note: Table 16 through Table 34 the LXT972A. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in operating conditions specified in 5.1 Electrical Parameters Table 16. Absolute Maximum Ratings Parameter ...
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... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. Table 21. I/O Characteristics - LED/CFG Pins Parameter Output Low Voltage Output High Voltage Input Current Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A 1 2 Min Typ Max – – ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet Table 22. 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot/Undershoot Jitter (measured differentially) 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. ...
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... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = ns. Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A 250ns ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet Figure 25. 100BASE-TX Transmit Timing - 4B Mode 0ns TXCLK TX_EN TXD<3:0> TPO CRS Table 26. 100BASE-TX Transmit Timing Parameters Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted ...
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... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 100 ns. Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet Figure 27. 10BASE-T Transmit Timing TX_CLK t 1 TXD, TX_EN, TX_ER t 3 CRS TPO Table 28. 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER setup to TX_CLK High TXD, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted ...
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... Table 30. 10BASE-T SQE Timing Parameters Parameter COL (SQE) Delay after TX_EN off COL (SQE) Pulse duration 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A Sym Min ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet Figure 30. Auto Negotiation and Fast Link Pulse Timing Clock Pulse TPO t1 Figure 31. Fast Link Pulse Timing FLP Burst TPO t4 Table 31. Auto Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse to Data pulse ...
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... MDIO hold after MDC, sourced by STA MDC to MDIO output delay, source by PHY MDC period 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A Sym Min ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet Figure 34. Power-Up Timing VCC MDIO,etc Table 33. Power-Up Timing Parameters Parameter Voltage threshold 2 Power Up delay 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. 2. Power Up Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the PHY comes ...
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... Register Definitions The LXT972A register set includes multiple 16-bit registers. Refer to register listing. • Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signaling for 10/100Mbps Auto- Negotiation” sections of the IEEE 802.3 standard. ...
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Table 36. Register Bit Map Reg Title B15 B14 B13 B12 Speed A/N Power Control Reset Loopback Select Enable 100Base- 100Base- 10Mbps 10Mbps 100Base- Status X Full X Half Full T4 Duplex Duplex Duplex Duplex PHY ...
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Table 36. Register Bit Map (Continued) Reg Title B15 B14 B13 B12 Status 10/100 Transmit Receive Collision Reserved Register #2 Mode Status Status Status Interrupt Reserved Enable Interrupt Reserved Status LED Config LED1 Trans. Transmit Reserved Control Low Pwr Bit ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet Table 37. Control Register (Address 0) Bit Name 1 = PHY reset 0.15 Reset 0 = Normal operation 1 = Enable loopback mode 0.14 Loopback 0 = Disable loopback mode 0.6 1 0.13 Speed Selection Auto-Negotiation 1 = Enable Auto-Negotiation Process 0.12 Enable 0 = Disable Auto-Negotiation Process 1 = Power-down 0.11 Power-Down 0 = Normal operation 1 = Electrically isolate PHY from MII ...
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... RO = Read Only LL = Latching Low LH = Latching High Table 39. PHY Identification Register 1 (Address 2) Bit Name PHY ID 2.15:0 The PHY identifier composed of bits 3 through 18 of the OUI. Number Read Only Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A Description Description 1 Type Default ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet Table 40. PHY Identification Register 2 (Address 3) Bit Name The PHY identifier composed of bits 19 through 24 of the 3.15:10 PHY ID number OUI. Manufacturer’s 3.9:4 6 bits containing manufacturer’s part number. model number Manufacturer’s 3.3:0 4 bits containing manufacturer’s revision number. ...
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... Pause operation enabled for full-duplex links. 4.10 Pause 0 = Pause operation disabled 100BASE-T4 capability is available 100BASE-T4 capability is not available. (The LXT972A does not support 100BASE-T4 but allows this bit to be set to 4.9 100BASE-T4 advertise in the Auto-Negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 transceiver could be switched in if this capability is desired.) 100BASE- Port is 100BASE-TX full-duplex capable ...
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... Bit Name 1 = Link Partner has ability to send multiple pages. 5.15 Next Page 0 = Link Partner has no ability to send multiple pages Link Partner has received Link Code Word from LXT972A. 5.14 Acknowledge 0 = Link Partner has not received Link Code Word from the LXT972A Remote fault. ...
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... Previous value of the transmitted Link Code Word equalled logic Toggle zero 7. Previous value of the transmitted Link Code Word equalled logic (T) one Message/ 7.10:0 Unformatted Code Field Read Only. R/W = Read/Write Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A Description Description 1 Type Default RO/ 0 ...
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... Link Partner has no additional next pages to send Acknowledge 1 = Link Partner has received Link Code Word from LXT972A 8.14 (ACK Link Partner has not received Link Code Word from LXT972A Message Page 1 = Page sent by the Link Partner is a Message Page 8.13 (MP Page sent by the Link Partner is an Unformatted Page ...
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... Write as zero, ignore on read. 1. R/W = Read /Write, LHR = Latches High on Reset Table 47. Status Register #2 (Address 17) Bit Name 17.15 Reserved Always LXT972A is operating in 100BASE-TX mode. 17.14 10/100 Mode 0 = LXT972A is not operating 100BASE-TX mode LXT972A is transmitting a packet. 17.13 Transmit Status 0 = LXT972A is not transmitting a packet LXT972A is receiving a packet. ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet Table 48. Interrupt Enable Register (Address 18) Bit Name 18.15:9 Reserved Write as 0; ignore on read. 18.8 Reserved Write as 0; ignore on read. Mask for Auto Negotiate Complete 18.7 ANMSK 1 = Enable event to cause interrupt not allow event to cause interrupt. Mask for Speed Interrupt 18 ...
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... Table 49. Interrupt Status Register (Address 19, Hex 13) (Continued) Bit Name 1 = MII interrupt pending. 19.2 MDINT MII interrupt pending. 19.1 Reserved Ignore. 19.0 Reserved Ignore 1. R/W = Read/Write Self Clearing. Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A Description 1 Type Default ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet Table 50. LED Configuration Register (Address 20, Hex 14) Bit Name 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) 0011 = Display Collision Status (Stretched) 0100 = Display Link Status (Continuous) ...
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... Port Rise Time Control 30.9:0 Reserved 1. Values are relative approximations. Not guaranteed or production tested. 2. R/W = Read/Write Datasheet 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A Description Description Ignore 1 = Forces the transmitter into low power mode. Also forces a zero-differential transmission Normal transmission 2.7 ns (default is pins TXSLEW<1:0> ...
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... LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 7.0 Package Specification Figure 37. LXT972A LQFP Package Specifications 64-Pin Low Profile Quad Flat Pack • Part Number - LXT972ALC Commercial Temperature Range (0ºC to +70ºC) Millimeters Dim Min A – 0.17 D 11. 11.85 E1 9.9 e 0.50 BSC L 0.45 L 1.00 REF ...