SST37VF010-70-3C-NH SST [Silicon Storage Technology, Inc], SST37VF010-70-3C-NH Datasheet - Page 2

• Manufacturer Part Number: SST37VF010-70-3C-NH
• Description: 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Many-Time Programmable Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

Byte-Program Operation
The SST37VF512/010/020/040 are programmed by using
an external programmer. The programming mode is acti-
vated by asserting 12V (±5%) on OE# pin and V
pin. The device is programmed using a single pulse (WE#
pin low) of 10 µs per byte. Using the MTP programming
algorithm, the Byte-Program process continues byte-by-
byte until the entire chip has been programmed. Refer to
Figure 10 for the flowchart and Figure 6 for the timing dia-
gram.
Chip-Erase Operation
The only way to change a data from a “0” to “1” is by electri-
cal erase that changes every bit in the device to “1”. The
SST37VF512/010/020/040 use an electrical Chip-Erase
operation. The entire chip can be erased in 100 ms (WE#
pin low). In order to activate erase mode, the 12V (±5%) is
applied to OE# and A
address and data pins are “don’t care”. The falling edge of
WE# will start the Chip-Erase operation. Once the chip has
been erased, all bytes must be verified for FFH. Refer to Fig-
ure 9 for the flowchart and Figure 5 for the timing diagram.
©2001 Silicon Storage Technology, Inc.
F
UNCTIONAL
Memory Address
B
LOCK
WE#
OE#
CE#
A 9
9
D
pins while CE# is low. All other
IAGRAM
Address Buffer
SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Control Logic
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
IL
on CE#
X-Decoder
2
Product Identification Mode
The Product Identification mode identifies the devices as
SST37VF512,
SST37VF040 and manufacturer as SST. This mode may
be accessed by the hardware method. To activate this
mode, the programming equipment must force V
(12V±5%) on address A
sequenced from the device outputs by toggling address
line A
TABLE 1: P
Design Considerations
The SST37VF512/010/020/040 should have a 0.1µF
ceramic high frequency, low inductance capacitor con-
nected between V
placed as close to the package terminals as possible.
OE# and A
tion of an Erase operation. OE# must remain stable at V
for the entire duration of the Program operation.
Manufacturer’s ID
Device ID
SST37VF512
SST37VF010
SST37VF020
SST37VF040
0
. For details, see Table 3 for hardware operation.
9
must remain stable at V
RODUCT
SST37VF010,
DD
DQ 7 - DQ 0
SuperFlash
Y-Decoder
I/O Buffers
Memory
and GND. This capacitor should be
9
I
DENTIFICATION
. Two identifier bytes may then be
Address
SST37VF020,
0000H
0001H
0001H
0001H
0001H
H
for the entire dura-
S71151-02-000 5/01
397 ILL B1.1
Data Sheet
Data
BFH
C4H
C5H
C6H
C2H
T1.2 397
and
397
H
H