MB85RC128PNF-G-JNERE1 FUJITSU [Fujitsu Component Limited.], MB85RC128PNF-G-JNERE1 Datasheet - Page 4

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MB85RC128PNF-G-JNERE1

Manufacturer Part Number
MB85RC128PNF-G-JNERE1
Description
Memory FRAM 128 K (16 K x 8) Bit I2C
Manufacturer
FUJITSU [Fujitsu Component Limited.]
Datasheet

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MB85RC128
■ I
• Start Condition, Stop Condition
Note : The FRAM device does not need the programming wait time (t
4
SCL
SDA
The I
data transfer can only be initiated by the bus master, which will also provide the serial clock for synchroni-
zation. The SDA signal should change while SCL is Low. However, as an exception, when starting and
stopping communication sequence, SDA is allowed to change while SCL is High.
• Start Condition
To start read or write operations by the I
is in the high state.
• Stop Condition
To stop the I
high state. In the reading operation, inputting the stop condition finishes reading and enters the standby
state. In the writing operation, inputting the stop condition finishes inputting the rewrite data.
2
C COMMUNICATION PROTOCOL
the write operation.
2
C bus is a two wire serial interface that uses a bidirectional data bus (SDA) and serial clock (SCL). A
2
C bus communication, change the SDA input from Low to High while the SCL input is in the
Start
2
C bus, change the SDA input from High to Low while the SCL input
WC
) after issuing the Stop Condition during
Stop
DS05–13110–3E

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