ax50424 AXSEM, ax50424 Datasheet - Page 26

• Manufacturer Part Number: ax50424
• Description: Advanced Multi-channel Single Chip Uhf Receiver
• Manufacturer: AXSEM

26
Circuit Description
5.14. Serial Peripheral Interface (SPI)
The
CLK, MOSI, MISO and SEL. Registers for setting up the
peripheral interface in all device modes.
When the interface signal SEL is pulled low, a 16 bit configuration data stream is expected on
the input signal pin MOSI, which is interpreted as D0...D7, A0...A6, R_N/W.
Data read from the interface appears on MISO.
Figure 3 shows a write/read access to the interface. The data stream is built of an address
byte including read/write information and a data byte. Depending on the R_N/W bit and
address bits A[6..0], data D[7..0] can be written via MOSI or read at the pin MISO.
R_N/W = 0 means read mode, R_N/W = 1 means write mode.
The read sequence starts with 7 bits of status information S[6..0] followed by 8 data bits.
The status bits contain the following information:
S6
PLL LOCK
SPI Timing
Version 1.3
MOSI
MISO
SCK
AX50424
SS
Tssd
Tss
R/W
can be programmed via a four wire serial interface according SPI using the pins
S5
FIFO OVER
A6
S6
Tck TchTcl
A5
S5
A4
S4
S4
FIFO UNDER
Ts
Figure 3 Serial peripheral interface timing
A3
S3
Th
Tco
A2
S2
S3
FIFO FULL
A1
S1
A0
S0
D7
D7
AX50424
S2
FIFO EMPTY
D6
D6
D5
D5
are programmed via the serial
D4
D4
S1
0
D3
D3
D2
D2
Datasheet AX50424
D1
D1
S0
0
D0
D0
Tsh
Tssz