ax50424 AXSEM, ax50424 Datasheet - Page 19

• Manufacturer Part Number: ax50424
• Description: Advanced Multi-channel Single Chip Uhf Receiver
• Manufacturer: AXSEM

5.3.
The SYSCLK pin outputs the reference clock signal divided by a programmable integer.
Divisions from 1 to 2048 are possible. For divider ratios > 1 the duty cycle is 50%. Bits
SYSCLK[3:0] in the
Outputting a frequency that is identical to the IF frequency (default 1 MHz) on the SYSCLK pin
is not recommended during receive operation, since it requires extensive decoupling on the
PCB to avoid interference.
5.4.
AX50424
RESET_N pin is required, prior to POR the RESET_N pin is disabled.
After POR the
After POR or reset all registers are set to their default values.
If the RESET_N pin is not used it must be tied to VDD_IO.
5.5.
The RF frequency generation subsystem consists of a fully integrated synthesizer, which
multiplies the reference frequency from the crystal oscillator to get the desired RF frequency.
The advanced architecture of the synthesizer enables frequency resolutions of 256 Hz, as well
as fast settling times of 5 – 50 µs depending on the settings (see section 4.3: AC
Characteristics). Fast settling times mean fast start-up, which enables low-power system
design.
The frequency must be programmed to the desired carrier frequency. The RF frequency shift
by the IF frequency that is required for RX operation, is automatically set when the receiver is
activated and does not need to be programmed by the user. The default IF frequency is 1
MHz. It can be programmed to other values. Changing the IF frequency and thus the centre
frequency of the digital channel filter can be used to adapt the blocking performance of the
device to specific system requirements.
The synthesizer loop bandwidth can be programmed, this serves two purposes:
Version 1.3
1. By SPI accesses: the bit RST in the
2. Via the RESET_N pin: A low pulse is applied at the RESET_N pin. With the rising edge of
1. Start-up time optimization. Start-up is faster for higher synthesizer loop bandwidths
2. RX spurious reception optimisation, phase-noise at 300kHz to 1MHz distance from the
Power-on-reset (POR) and RESET_N Input
SYSCLK Output
RF Frequency Generation Subsystem
RESET_N the device goes into its operational state.
LO and thus spurious reception improves with lower synthesizer loop bandwidths
has an integrated power-on-reset block. No external POR circuit or signal at the
AX50424
PINCFG1
can be reset in two ways:
register set the divider ratio. The SYSCLK output can be disabled.
PWRMODE
register is toggled.
Table of Contents
Datasheet AX50424
19