ax500-1cs896i Actel Corporation, ax500-1cs896i Datasheet - Page 30
ax500-1cs896i
Manufacturer Part Number
ax500-1cs896i
Description
Axcelerator Family Fpgas
Manufacturer
Actel Corporation
Datasheet
1.AX500-1CS896I.pdf
(226 pages)
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Table 2-15 • Macros for Single-Ended I/O Standards
2 -1 6
Standard
LVTTL
3.3V PCI
3.3V PCI-X
LVCMOS25
LVCMOS18
LVCMOS15 (JESD8-11)
Axcelerator Family FPGAs
• Pull-up and pull-down variations of the INBUF,
inputs (e.g. INBUF_LVDS) or a pair of differential
outputs (e.g. OUTBUF_LVPECL).
BIBUF, and TRIBUF macros. These are available
only with TTL and LVCMOS thresholds. They can
be used to model the behavior of the pull-up and
pull-down resistors available in the architecture.
Whenever an input pin is left unconnected, the
output pin will either go high or low rather than
unknown. This allows users to leave inputs
V
3.3V
3.3V
3.3V
1.5V
2.5V
1.8V
CCI
CLKBUF, HCLKBUF
INBUF,
OUTBUF,
OUTBUF_S_8, OUTBUF_S_12, OUTBUF_S_16, OUTBUF_S_24,
OUTBUF_H_8, OUTBUF_H_12, OUTBUF_H_16, OUTBUF_H_24,
TRIBUF,
TRIBUF_S_8, TRIBUF_S_12, TRIBUF_S_16, TRIBUF_S_24,
TRIBUF_H_8, TRIBUF_H_12, TRIBUF_H_16, TRIBUF_H_24,
BIBUF,
BIBUF_S_8, BIBUF_S_12, BIBUF_S_16, BIBUF_S_24,
BIBUF_H_8, BIBUF_H_12, BIBUF_H_16, BIBUF_H_24,
CLKBUF_PCI, HCLKBUF_PCI,
INBUF_PCI,
OUTBUF_PCI,
TRIBUF_PCI,
BIBUF_PCI
CLKBUF_PCI-X,
HCLKBUF_PCI-X,
INBUF_PCI-X,
OUTBUF_PCI-X,
TRIBUF_PCI-X,
BIBUF_PCI-X
HCLKBUF_LVCMOS25,
INBUF_LVCMOS25,
OUTBUF_LVCMOS25,
TRIBUF_LVCMOS25,
BIBUF_LVCMOS25
HCLKBUF_LVCMOS18,
INBUF_LVCMOS18,
OUTBUF_LVCMOS18,
TRIBUF_LVCMOS18,
BIBUF_LVCMOS18
CLKBUF_LVCMOS15,
HCLKBUF_LVCMOS15,
INBUF_LVCMOS15,
OUTBUF_LVCMOS15,
TRIBUF_LVCMOS15,
BIBUF_LVCMOS15
CLKBUF_LVCMOS25,
CLKBUF_LVCMOS18,
v2.6
Table
page 2-17
differentiated by I/O standard, type, slew rate, and drive
strength.
• DDR_REG macro. It can be connected to any I/O
2-15,
unconnected without having the negative effect
on simulation of propagating unknowns.
standard input buffers (i.e. INBUF) to implement a
double data rate register. Designer software will
map it to the I/O module in the same way it maps
the other registers to the I/O module.
Table 2-16 on page
list
Macro Names
all
the
available
2-17, and
macro
Table 2-17 on
names
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