ne56625-20 NXP Semiconductors, ne56625-20 Datasheet - Page 10

• Manufacturer Part Number: ne56625-20
• Description: Ne56625-20 System Reset With Watchdog Timer
• Manufacturer: NXP Semiconductors

from the microprocessor, allowing it to function normally. The system
Philips Semiconductors
Timing diagram
The timing diagram shown in Figure 17 depicts the operation of the
device. Letters indicate events on the TIME axis.
A: At start-up ‘A’, the V
and Battery Check (BC) voltages initially rise, but then abruptly
return to a LOW state. This is due to V
that activates the internal bias circuitry, asserting RESET and BC.
B: Just before ‘B’, the C
by, and coincident to, V
this level the device initiates the RESET delay time, t
continues to rise above V
C: At ‘C’, V
voltage BC detection threshold. At this level, the BC output goes
HIGH. BC output follows V
D: At ‘D’, V
has ramped up to its upper detect level. At this point, an internal
ramp discharge transistor activates, discharging C
is still in effect since the delay time has not elapsed.
E: At ‘E’, the delay time has elapsed and the device removes the
hold on the reset. RESET goes HIGH.
In a microprocessor based system these events remove the reset
must send clock signals to the Watchdog Timer often enough to
prevent C
signals from being generated. Each clock signal discharges C
E–F: Midway between ‘E’ and ‘F’, the CLK signals cease allowing
the C
reset signals are generated (RESET goes LOW). The device
attempts to come out of reset as the C
finally does come out of reset when CLK signals are reestablished
after two attempts of C
G–I: Immediately before ‘G’, falling V
BC outputs to sag. CLK signals are still being received, and C
2003 Oct 15
System reset with Watchdog timer
T
voltage to ramp up to its RESET threshold at ‘F’. At this time
T
from ramping up to the C
CC
CC
rises to the threshold level of V
is above the undervoltage detect threshold and C
T
CC
.
CC
SHR
T
reaching the threshold level of V
CC
voltage starts to ramp up. This is caused
voltage begins to rise. Also the RESET
.
to its normal operating level.
T
threshold, to prevent reset
CC
T
CC
voltage is discharged, and
reaching the level of 0.8 V
causes the RESET and
SHB
T
, the upper
. Reset assertion
PLH
. V
SHR
CC
T
T
.
. At
is
T
10
frequency than those following event ‘D’. The frequency is above the
Q: At event ‘Q’ V
and as a result may exhibit a slight rise to something less than 0.8 V.
within normal operating range. V
battery check undervoltage threshold is reached. At that time (G),
BC output goes LOW. V
undervoltage threshold is reached. At this point (H), reset is
asserted and RESET goes LOW. Between ‘H’ and ‘I’, V
rise, however, C
V
delay is initiated.
J–K: At ‘J’, the BC output goes HIGH when V
Between ‘J’ and ‘K, C
‘K’, RESET delay time elapses and the reset is released and
RESET goes HIGH.
L–M: From ‘L’ to ‘M’, the R
the Watchdog timer by shorting C
open or taken to V
configuration enables the Watchdog timer.
N: After ‘N’, normal CLK signals are received, but at a lower
minimum frequency required to keep the device from outputting
reset signals.
O–P: At ‘O’, V
no reset signals are output. At event ‘P’, the V
causing RESET and BC to also fall.
threshold point is reached, and at that level reset signal is outputted
(RESET to a LOW state).
R: At event ‘R’ the V
normal internal circuit bias is no longer able to maintain a RESET,
As V
CC
reaches the V
CC
decays even further, RESET also decreases to zero.
CC
T
voltage does not start to ramp up until ‘I’, when
CC
CC
SHR
is normal, CLK signals are being received, and
T
with a resistor of 1 M or greater. This
sags to the point where the V
CC
upper reset threshold. Also, the RESET
reaches the upper threshold level again. At
CC
voltage has deteriorated to a level where
sags still further until V
CT
is shorted to ground. This disables
CC
T
to ground. At other times R
continues to sag until the V
NE56625-20
CC
CC
starts falling,
SLR
rises to V
SLR
reset
CC
undervoltage
Product data
starts to
SHB
CT
SLB
.
is