hb28b128mm2 Renesas Electronics Corporation., hb28b128mm2 Datasheet - Page 51
hb28b128mm2
Manufacturer Part Number
hb28b128mm2
Description
Multimediacard 16 Mbyte/32 Mbyte/64 Mbyte/128 Mbyte
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.HB28B128MM2.pdf
(90 pages)
- Current page: 51 of 90
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The host command and the card response are clocked out with the rising edge of the host clock. The delay
between host command and card response is N
for host command CMD3:
There is just one Z bit period followed by P bits pushed up by the responding card. The following timing
diagram is relevant for all host commands followed by a response, except CMD1, CMD2 and CMD3:
• Card identification and card operation conditions timing
The card identification (CMD2) and card operation condition (CMD1) timing are processed in the open-
drain mode. The card response to the host command starts after exactly N
• Last card response - next host command timing
After receiving the last card response, the host can start the next command transmission after at least N
clock cycles. This timing is relevant for any host command.
CMD
CMD
CMD
CMD
S T
S T
S T
S T
Timing Response End to Next CMD Start (Data Transfer Mode)
Host command
Host command
Host active
Host active
Host command
content
content
Command Response Timing (Data Transfer Mode)
Host active
Command Response Timing (Identification Mode)
content
Identification Timing (Card Identification Mode)
Card active
content
Response
CRC E Z
CRC E Z Z P
CRC E Z
CRC E Z
CR
N
N
clock cycles. The following timing diagram is relevant
N
* * * * * *
CR
CR
ID
N
* * *
cycles
cycles
* * * * * *
cycles
RC
* * *
HB28H016/D032/B064/B128MM2
cycles
P
Z
Z
S T
S T
S T
Card active
Z
S T
Card active
Card active
Response
Response
content
content
CID or OCR
Host command
Rev.5.0, Jan. 2003, page 49 of 88
ID
content
content
Host active
clock cycles.
CRC E Z Z Z
CRC E Z Z Z
CRC E
Z Z Z
RC
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