k4h560838f Samsung Semiconductor, Inc., k4h560838f Datasheet - Page 11
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k4h560838f
Manufacturer Part Number
k4h560838f
Description
256mb F-die Ddr Sdram Specification
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4H560838F.pdf
(23 pages)
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IDD7A : Operating current: Four bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
4. Timing patterns
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
2. Timing patterns
DDR SDRAM 256Mb F-die (x8, x16)
- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
- A2(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
- AA (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 2*tCK, tRC = 8*tCK, tRAS = 6*tCK
- B3(166Mhz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge
- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
- A2 (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
- AA (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 2*tCK, tRC = 8*tCK, tRAS = 6*tCK
- B3(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC = 10*tCK, tRAS=7*tCK
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Read : A0 N R0 N N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
changing. lout = 0mA
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
Read : A0 N R0 N N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
per clock cycle. lout = 0mA
*50% of data changing at every burst
*50% of data changing at every burst
*50% of data changing at every burst
*50% of data changing at every burst
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 1.3 October, 2004
DDR SDRAM