hi-3210 Holt Integrated Circuits, Inc., hi-3210 Datasheet - Page 21

• Manufacturer Part Number: hi-3210
• Description: Arinc 429 Data Management Engine / Octal Receiver / Quad Transmitter
• Manufacturer: Holt Integrated Circuits, Inc.

Each of the four ARINC 429 transmit channels has its
own transmit controller. The controller is user-
programmed to output ARINC labels in a predefined
order and repetition rate. A sequence of up to 256 ARINC
labels may be transmitted before repeating the sequence.
A descriptor table with up to 256 entries (descriptors) is
compiled by the user to define the sequence of ARINC
429 messages transmitted on each channel. When the
RUN/
asserted, the controller compiles the first 32-bit ARINC
word from the instructions given by the first descriptor
and then transmits it. A Transmit Sequence Pointer then
increments to the next descriptor in the table and the
process is repeated for Descriptor number 2.
ARINC 429 messages continue to be compiled and
transmitted until the last descriptor in the table. The end
of the table is marked by a special descriptor if not all 256
entries are needed. The Sequence Pointer is then reset
to zero.
A Repetition Rate Counter is used to time the start of the
next transmission cycle.
The value of each ARINC 429 label transmitted in the
sequence is defined by its eight-byte descriptor. The
descriptor consists of one “Action byte” and one “Value”
byte for each of the four bytes that make up the ARINC
429 transmitted label.
The four pairs of Action and Value bytes describe where
the data for each byte may be found. Different op-codes
allow the data source to be host CPU populated fixed
ARINC 429 Transmit Scheduler
ARINC 429 Transmit Descriptor table
Repetion Rate
Repetition rate
STOP
(Memory Addresses shown
Register
counter
for ARINC Tx channel 0)
bit in the ARINC TX Control Register is
Sequence
pointer
0 0 0
0x4028
0x4020
0x4018
0x4010
0x4008
0x4000
0x47FF
0x47F8
0x47F0
HOLT INTEGRATED CIRCUITS
Sequence 255 Descriptor Frame
Sequence 254 Descriptor Frame
Sequence 5 Descriptor Frame
Sequence 4 Descriptor Frame
Sequence 3 Descriptor Frame
Sequence 2 Descriptor Frame
Sequence 1 Descriptor Frame
Sequence 0 Descriptor Frame
HI-3210
21
The user is responsible for construction of the descriptor
table and for setting the Repetition Rate prior to asserting
RUN/STOP. Facilities exist for immediate cycle repetition
and for single-cycle operation.
The byte content of each ARINC 429 message
transmitted is user defined by the descriptor contents.
Data bytes may be sourced from the host CPU / auto-
initialization EEPROM (immediate data) or from the
ARINC 429 receive memory (ARINC indexed). This
allows received ARINC data to be re-transmitted on
another bus with or without filtering, label byte re-
assignment or data modification. It also allows data from
multiple ARINC 429 receive buses to be re-packetized
into new ARINC 429 transmitted messages.
Conditional transmission control allows sequenced words
to be skipped if no new data is available.
Each ARINC 429 transmit channel is independently
configured with its own ARINC 429 TX Control Register,
ATXCR0-3, as previously described.
values, or values from specific locations within the ARINC
429 receive memory. Action byte 1 also has one
additional op-code to facilitate sequence flow control.
The construction of Action and Value bytes are described in
the next section.
Action Byte 4
Action Byte 3
Action Byte 2
Action Byte 1
Value Byte 4
Value Byte 3
Value Byte 2
Value Byte 1