92hd89c Integrated Device Technology, 92hd89c Datasheet - Page 73
92hd89c
Manufacturer Part Number
92hd89c
Description
Six Channel Hd Audio Codec
Manufacturer
Integrated Device Technology
Datasheet
1.92HD89C.pdf
(314 pages)
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92HD89C
Six channel HD Audio codec optimized for low power
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
IDT™ CONFIDENTIAL
Field Name
PortB
PortA
Field Name
Rsvd
D5
D4
Reg
Reg
Get
Set
Set
7.4.25. AFG (NID = 01h): VSPwrState
7.4.26. AFG (NID = 01h): AnaPort
Byte 4 (Bits 31:24)
Byte 4 (Bits 31:24)
Bits
1
Port B usage: 0 = connected as an output, 1 = either not connected or connect-
ed as an input.
0
Port A usage: 0 = connected as an output, 1 = either not connected or connect-
ed as an input.
Bits
31:2
Reserved.
1
Vendor specific D5 power state, only entered once the part is already in D3cold
(this bit must be set before the command to enter D3cold). If set, this bit over-
rides the D4 bit (bit 0). Includes the power savings of D4, but additionally pow-
ers down GPIO pins, the VAG amp, and the HP amps. Exits this power state
via POR or rising edge of Link Reset.
0
Vendor specific D4 power state, only entered once the part is already in D3cold
(this bit must be set before the command to enter D3cold). If the D5 bit (bit 1)
is set, this bit is overridden. Includes the power savings of D3cold, but addi-
tionally powers down the HDA interface (no responses). Exit this power state
via POR or rising edge of Link Reset.
Byte 3 (Bits 23:16)
Byte 3 (Bits 23:16)
R/W
RW
RW
R/W
R
RW
RW
FD800h
Default
0h
0h
Default
00000000h
0h
0h
73
Byte 2 (Bits 15:8)
Byte 2 (Bits 15:8)
7EDh
Reset
POR
POR
Reset
N/A (Hard-coded)
POR - ELR
POR - ELR
Byte 1 (Bits 7:0)
Byte 1 (Bits 7:0)
7ECh
7D8h
V 0.91 08/09
92HD89C
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