ak7746 ETC-unknow, ak7746 Datasheet - Page 56

• Manufacturer Part Number: ak7746
• Description: Audio With 5-channel 24-bit Input
• Manufacturer: ETC-unknow

b) SO data read (during run phase)
allows DRDY to go to "H", and data is output synchronized with the falling edge of SCLK. When SI goes to "H", DRDY goes to "L"
to wait for the next command. Once DRDY goes to "H", the data of the last @MICR command immediately before DRDY goes to "H"
will be held until SI goes to "H" or read out 24-bit data with SCLK, and subsequent commands will be rejected. A maximum of 24 bits
are output from SO.
microcontroller cannot read out at SCLK rising edge, it should ignore the last 1bit (D0).
[MS0369-E00]
Note) In the case of read out 24-bit data, DRDY falls down when 24
[ASAHI KASEI]
S_RESET
@MICR
DRDY
SCLK
RQ
SI
SO
SO outputs data on DBUS (data bus) of the DSP section. Data is set when @MICR the DST field specifies. Setting of data
D23 D22 D21* * * * * D3 D2 D1 D0
Data1
24 SCLK Clock
Fig.8-31 SO read (during RUN phase)
- 56 -
th
SCLK rising edge and SO output bit is not stable. So, if the
D23 D22 D21D20 D19 D18
Less than 24 SCLK
Data2
[AK7746]
2004/12