ak7746 ETC-unknow, ak7746 Datasheet - Page 34

• Manufacturer Part Number: ak7746
• Description: Audio With 5-channel 24-bit Input
• Manufacturer: ETC-unknow

(3) Power supply startup sequence
begins to generate the internal master clock by setting to INIT_RESET = “H”. The interface of the AK7746 cannot accept data
before the PLL locks; it must wait at least 15ms from INIT_RESET = “H”. Note 3)
Normally, INIT_RESET setting is only done at power-on.
[MS0369-E00]
[ASAHI KASEI]
INIT_RESET = “L” initializes all control registers. Note 1), Note 2). VREF (Analog reference level) of the AK7746 is set up and
AVDD
DVDD
XTI
(internal PLLCLK)
CLKO1,CLKO2
At the rise of AVDD and DVDD, INIT_RESET and S_RESET should be set to “L”.
Note 3): In case of CKS[1:0] = 0h then waiting time is 15ms. CKS[1:0] = 1h or 2h then waiting time is 22ms.
Note 1): To confirm initialization power up and master clock (XTI) supplied.
Note 2): Set to INIT_RESET = “H” after setting the oscillation when a crystal oscillator is used.
INIT_RESET
S_RESET
NOTE: Do not stop the system clock (slave mode: XTI, LRCLK_I, BITCLK_I (CLK2S mode : LRCLK_I, BITCLK_I),
master mode: XTI) except when S_RESET = "L". If these clock signals are not supplied, excess current will flow due to
dynamic logic that is used internally, and an operation failure may result.
Don’t set S_RESET ="H" during INIT_RESET ="L", unless its crystal oscillator will stop or be in unstable.
This setting time may differ depending on the crystal oscillator and its external circuit.
Power OFF
When a crystal oscillator
is used, ensure stable
oscillation in this period.
Fig.8-6 Power supply startup sequence
Before PLL stable
Inhibit to transfer data
(15ms)
- 34 -
CLKO output start
12ms(MAX)*
Enable to transfer command or
DSP Program code.
22ms(MAX)* : CKS[1:0] = 1h or 2h
( 15ms : CKS[1:0] = 0h )
[AK7746]
2004/12