ak7746 ETC-unknow, ak7746 Datasheet - Page 28

• Manufacturer Part Number: ak7746
• Description: Audio With 5-channel 24-bit Input
• Manufacturer: ETC-unknow

64h
Command
W
3) CONT2 : Conditional jump, instruction setting. ( See 3. Block diagram )
Recommend changing this register at the system reset state ( S_RESET =”L”).
Note) Underlines of the
[MS0369-E00]
[ASAHI KASEI]
Code
D7 : JX2_E (See. 3. Block diagram )
D6 : JX1_E (See. 3. Block diagram )
D5 : JX0_E (See. 3. Block diagram )
D4 : SSDIN4 DSP instruction select.
D3 : SSDIN3 DSP insturuction select
D2 : SWQMD (See 3. Block diagram )
D1 : TEST
D0 : Always input 0
74h
R
0: Normal operation (SDIN4)
1: JX2 is enable. (SDIN4 can not be read)
0: Normal operation (SDIN3)
1: JX1 is enable. (SDIN3 can not be read)
0: Normal operation (SDIN1)
1: JX0 is enable. (SDIN1 can not be read)
0: ODRB and MSRG are enabled (@SWSDIN4_N=0) / INL4 and MSRG are enabled (@SWSDIN4_N=1)
1: INL4 and INR4 (Digital input of SDIN4 ) are enabled.
0: TDR2 and TDR3 (DR2 and DR3 through output ) are enabled
1: INL3 and INR3 ( Digital input of SDIN3 ) are enabled.
0: Normal operation
1: The digital output of ADCM connects to SDOUT4.
0: Normal operation
1: TEST MODE ( Do NOT use this.)
When SRC data loads to DBUS, TDR2 and TDR3 data is changed to INL3 and INR3 data.
CONT2
Name
SSDIN4
0
0
1
JX2_E
~
D7
mean default setting.
SWSDIN4_N
(CONT4 D6)
JX1_E
D6
0
1
×
JX0_E
D5
- 28 -
SSDIN4
SRC field
ODRB
D4
INL4
INL4
SSDIN3
D3
SWQMD
D2
SRC field
MSRG
MSRG
INR4
TEST
D1
D0
×
[AK7746]
2004/12
000 000X
Default