ak4614 ETC-unknow, ak4614 Datasheet
ak4614
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ak4614 Summary of contents
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... The AK4614 is a single chip audio CODEC that includes six ADC channels and twelve DAC channels. The converters are designed with Enhanced Dual Bit architecture for the ADC’s, and Advanced Multi-Bit architecture for the DAC, enabling very low noise performance. Fabricated on a low power process, the AK4614 operates off ...
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Master clock - Slave mode: 256fs, 384fs or 512fs (Normal Speed Mode: fs=32kHz ∼ 48kHz) - Master mode: 256fs or 512fs 6. 4-wire Serial and I 7. Power Supply - Analog Power Supply: AVDD1, AVDD2 = 3.0 ∼ 3.6V ...
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Block Diagram LIN1+ / LIN1 LIN1- RIN1+ / RIN1 RIN1- LIN2+ / LIN2 LIN2- RIN2+ / RIN2 RIN2- LIN3+ / LIN3 LIN3- RIN3+ / RIN3 RIN3- LOUT1+ / LOUT1 SCF1 LOUT1- ROUT1+ / ROUT1 SCF1 ROUT1- LOUT2+ / LOUT2 ...
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... RIN2- 73 LIN3+ / LIN3 74 LIN3- 75 VSS1 76 AVDD1 77 VREFH1 78 VCOM 79 RIN3+ / RIN3 80 RIN3- MS1025-E-00 -40 ∼ +105°C 80pin LQFP(0.5mm pitch) Evaluation Board for AK4614 80 pin LQFP (TOP VIEW) Figure 2. Pin Layout - LOUT2+ / LOUT2 39 ROUT1- 38 ROUT1+ / ROUT1 37 LOUT1- 36 LOUT1+ / LOUT1 35 DVMPD 34 SDTI6 33 ...
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... Single or Diff Single or Diff I2S, LJ, RJ(16/20/24bit), TDM Fs=48kHz Yes No Yes -40 ∼ +105°C 80pinLQFP AK4614 No 3.0 ∼ 3.6V 3.0 ∼ 3.6V 1.6 ∼ 2.0V No 1.6 ∼ 3.6V 1.6 ∼ 3.6V AK4614 192k / 192k Single Differential : 97 / 100 Single: 103 / 105 Differential: 104 / 108 256 level 400k I2C, 4wire 2008/10 ...
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... O Master Clock Output Pin PDN I Power-Down & Reset Pin 19 When “L”, the AK4614 is powered-down and the control registers are reset to default state. If the state of CAD1-0 changes, then the AK4614 must be reset by PDN. 20 XTO O X’tal Output Pin XTI I X’tal Input Pin ...
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No. Pin Name I/O LOUT1+ O Lch Analog Positive Output 1 Pin (DOE1 bit = “H”) 36 LOUT1 O Lch Analog Output 1 Pin (DOE1 bit = “L”) 37 LOUT1- O Lch Analog Negative Output 1 Pin (When DOE1 bit ...
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No. Pin Name I/O RIN1- - Rch Analog Negative Input 1 Pin (When DIE1 bit = “L”, this pin must be open Note 3 LIN2+ I Lch Analog Positive Input 2 Pin (DIE2 bit = “H”) 69 LIN2 ...
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... Do not turn off only the AK4614 under the condition that a surrounding device is powered on and the I2C bus is in use. WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. ...
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AVDD1=AVDD2=TVDD1=TVDD2=3.3V, DVDD =1.8V; VSS1=VSS2=0V; VREFH1=AVDD1, VREFH2=AVDD2; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 48kHz, 20Hz~40kHz at fs=96kHz, 20Hz~40kHz at fs=192kHz; unless otherwise specified) Parameter ADC Analog Input Characteristics (single inputs) Resolution S/(N+D) fs=48kHz BW=20kHz fs=96kHz BW=40kHz fs=192kHz ...
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DAC Analog Output Characteristics (differential outputs) S/(N+D) fs=48kHz BW=20kHz fs=96kHz BW=40kHz fs=192kHz BW=40kHz DR (-60dBFS with A-weighted) S/N (A-weighted) Interchannel Isolation Interchannel Gain Mismatch Gain Drift Output Voltage AOUT=0.65xVREFH2 Load Resistance Load Capacitance Power Supply Rejection Note 7. PSR is ...
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AVDD1=AVDD2=3.0∼ 3.6V, DVDD=1.6∼ 2.0V, TVDD1=TVDD2=1.6∼ 3.6V; DEM=OFF) Parameter ADC Digital Filter (Decimation LPF): 13) ±0.1dB Passband (Note Stopband Passband Ripple Stopband Attenuation Group Delay Distortion Group Delay ADC Digital Filter (HPF): 13) −3dB Frequency Response (Note ...
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AVDD1=AVDD2=3.0∼ 3.6V, DVDD=1.6∼ 2.0V, TVDD1=TVDD2=1.6∼ 3.6V; DEM=OFF) Parameter ADC Digital Filter (Decimation LPF): 13) ±0.1dB Passband (Note Stopband Passband Ripple Stopband Attenuation Group Delay Distortion Group Delay ADC Digital Filter (HPF): 13) −3dB Frequency Response (Note ...
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AVDD1=AVDD2=3.0∼3.6; DVDD=1.6∼2.0V; TVDD1=TVDD2=1.6∼3.6V) Parameter TVDD1,TVDD2 ≤2.2V High-Level Input Voltage (TST2, M/S, PDN, MCKI, LRCK, BICK, SDTI1, SDTI2, SDTI3, SDTI4,SDTI5, SDTI6, DVMPD pins) (TST1,TST3,TST4,TST5,CAD0,CAD1,I2C, CSN,CCLK, CDTI pins) Low-Level Input Voltage (TST2, M/S, PDN, MCKI, LRCK, BICK, SDTI1, SDTI2, SDTI3, SDTI4,SDTI5, ...
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AVDD1=AVDD2=3.0∼3.6; DVDD=1.6∼2.0V; TVDD1=1.6∼3.6V, TVDD2=1.6∼3.6V; C unless otherwise specified) Parameter Master Clock Timing Crystal Resonator Frequency MCKO Output Frequency (TVDD1 ≥3.0V) Duty External Clock 256fsn: Pulse Width Low Pulse Width High 384fsn: Pulse Width Low Pulse Width High 512fsn, 256fsd, ...
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Parameter LRCK Timing (Master Mode) Stereo mode (TDM0 bit = “0”, TDM1 bit = “0”) Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle TDM512 mode (TDM0 bit = “0”, TDM1 bit = “1”) LRCK frequency “H” time ...
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Parameter Audio Interface Timing (Slave mode) Stereo mode (TDM0 bit = “0”, TDM1 bit = “0”) (TVDD1= 1.6V∼3.6V) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” BICK “↑” to LRCK Edge LRCK to SDTO(MSB) ...
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Parameter Audio Interface Timing (Master mode) Stereo mode (TDM0 bit = “0”, TDM1 bit = “0”) (TVDD1= 1.6V∼3.6V) BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO SDTI Hold Time SDTI Setup Time (TVDD1= 3.0V∼3.6V) BICK Frequency ...
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... PDN “↑” to SDTO valid Note 22. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 23. The AK4614 can be reset by setting the PDN pin to “L” upon power-up. Note 24. These cycles are the numbers of LRCK rising from the PDN pin rising. ...
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Timing Diagram MCKI LRCK BICK Figure 3. Clock Timing (TDM1/0 bit = “00” & Slave mode) MCKI LRCK BICK Figure 4. Clock Timing (Except TDM1/0 bit = “00” & Slave mode) MS1025-E-00 1/fCLK tCLKH tCLKL 1/fsn, 1/fsd, 1/fsq tdLRKH ...
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MCKI tCLKH MCKO tdMCKH LRCK tdLRKH BICK Figure 5. Clock Timing (TDM1/0 bit = “00” & Master mode) MCKI tCLKH MCKO tdMCKH LRCK BICK Figure 6. Clock Timing (Except TDM1/0 bit = “00” & Master mode) MS1025-E-00 1/fCLK tCLKL 1/fMCK ...
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LRCK BICK tLRS SDTO SDTI Figure 7. Audio Interface Timing (TDM1/0 bit = “00” & Slave mode) LRCK BICK SDTO SDTI Figure 8. Audio Interface Timing (Except TDM1/0 bit = “00” & Slave mode) MS1025-E-00 tBLR tLRB tSDS tSDH tBLR ...
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LRCK tMBLR BICK SDTO SDTI Figure 9. Audio Interface Timing (TDM1/0 bit = “00” & Master mode) LRCK tMBLR BICK SDTO SDTI Figure 10. Audio Interface Timing (Except TDM1/0 bit = “00” & Master mode) MS1025-E-00 tBSD tSDS tSDH tBSS ...
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CSN tCSH CCLK CDTI CDTO Figure 11. WRITE Command Input Timing (4-wire Serial mode) CSN CCLK CDTI D2 CDTO Figure 12. WRITE Data Input Timing (4-wire Serial mode) MS1025-E-00 tCSS tCCKL tCCKH tCDS C1 C0 Hi-Z tCSH D1 D0 Hi-Z ...
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CSN CCLK CDTI A1 CDTO Figure 13. Read Data Output Timing1(4-wire Serial mode) CSN CCLK CDTI CDTO D2 Figure 14. Read Data Output Timing2(4-wire Serial mode) MS1025-E-00 A0 tDCD Hi-Z tCSH VIH VIL VIH VIL ...
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SDA tBUF tLOW SCL tHD:STA Stop Start PDN SDTO MS1025-E-00 tR tHIGH tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure 15 Bus mode Timing tPD tPDV Figure 16. Power-down & Reset Timing - 26 - VIH VIL tSP VIH ...
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... CKS1-0 bits and DFS1-0 bits up. After exiting reset at power-up in slave mode, the AK4614 is in power-down mode until MCLK and LRCK are input. If the clock is stopped, click noise occurs when restarting the clock. Mute the digital output externally if the click noise influences system applications ...
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Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode) Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz Table 7. System Clock Example (Auto Setting Mode) MS1025-E-00 ...
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... X’tal Note: External capacitance depends on the crystal oscillator (Typ. 10pF) TVDD1 should be used in the range of 3.0 ~ 3.6V in X’tal mode. MS1025-E-00 XTI AK4614 XTO Figure 17. External clock mode Note: Input clock must not exceed TVDD1. XTI AK4614 XTO Figure 18. X’tal mode - 29 - 2008/10 ...
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... DIE1-3 bits = “0”. In differential input mode, two input pins must not be connected to a signal input in combination with a VCOM voltage. When single-end input mode, L/RIN1-3- pins should be open, because L/RIN1-3- pins output an invert signal of the input signal. The AK4614 includes an anti-aliasing filter (RC filter) for both differential input and the single-end input. ...
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... Master Clock Output The AK4614 has a master clock output pin. If DIV bit = “1”, the MCKO pin output the frequency divided in half. Table 9. The select of Master clock output frequency ■ Master Mode and Slave Mode Master Mode and Slave Mode are selected by setting the M/S pin. (Master Mode= “ ...
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Audio Serial Interface Format When TDM1-0 bits = “00”, ten modes can be selected by the DIF2-0 bits as shown in is MSB-first, 2’s compliment format. The data SDTO1-3 is clocked out on the falling edge of BICK and ...
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The audio serial interface format in TDM mode is set by the TDM1-0 bits. Five modes can be selected by the DIF2-0 bits as shown in Table 12. In all modes the serial data is MSB-first, 2’s compliment format. The ...
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Mode M/S TDM1 TDM0 DIF2 ...
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LRCK BICK(64fs) SDTO( SDTI(i) Don’t Care 15 14 SDTO-23:MSB, 0:LSB; SDTI-15:MSB, 0:LSB Lch Data LRCK BICK(64fs) SDTO( SDTI(i) Don’t Care SDTO-23:MSB, 0:LSB; SDTI-19:MSB, ...
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LRCK BICK(64fs) SDTO( SDTI( 23:MSB, 0:LSB LRCK(Mode15) LRCK(Mode10) BICK(512fs) SDTO1( BICK 32 BICK 32 BICK SDTI1( ...
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LRCK(Mode18) LRCK(Mode13) BICK(512fs) SDTO1( BICK 32 BICK 32 BICK SDTI1( BICK 32 BICK 32 ...
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LRCK (Mode26) LRCK (Mode21) BICK(256fs SDTO1( BICK 19 18 SDTI1( BICK 19 18 SDTI2( BICK LRCK (Mode27) LRCK (Mode22) BICK(256fs SDTO1( BICK 23 22 SDTI1( BICK ...
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LRCK (Mode28) LRCK (Mode23) BICK(256fs SDTO1( BICK 23 22 SDTI1( BICK 23 22 SDTI2( BICK LRCK (Mode29) LRCK (Mode24) BICK(256fs) 23 SDTO1( BICK 23 SDTI1( BICK 23 SDTI2(i) ...
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LRCK (Mode35) LRCK (Mode30) BICK(128fs SDTO1( SDTO2( SDTI1( SDTI2( SDTI3(i) LRCK (Mode36) LRCK (Mode31) BICK(128fs SDTO1( SDTO2( SDTI1(i) SDTI2( SDTI3(i) ...
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LRCK (Mode37) LRCK (Mode32) BICK(128fs SDTO1( SDTO2( SDTI1( SDTI2( SDTI3(i) LRCK (Mode38) LRCK (Mode33) BICK(128fs SDTO1( SDTO2( SDTI1(i) SDTI2( SDTI3( ...
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LRCK (Mode39) LRCK (Mode34) BICK(128fs) 22 SDTO1(o) 23 SDTO2(o) 23 SDTI1(i) SDTI2(i) 23 SDTI3(i) 23 MS1025-E-00 128 BICK BICK 32 BICK BICK 32 BICK ...
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... Zero Detection The AK4614 has two pins for zero detect flag outputs. Zero detect function is enabled when the OVFE bit is set to “0”. Channel grouping can be selected by the DZFM3-0 bits. and the DZF2 pin corresponds to the group 2 channels. DZF1 is AND operation of all twelve channels and DZF2 is disabled (“ ...
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... Digital Attenuator AK4614 has a channel-independent digital attenuator (256 levels, 0.5dB steps). Attenuation level of each channel can be set by each the ATT7-0 bits (Table Transition time between set values of ATT7-0 bits can be selected by the ATS1-0 bits values is the soft transition in Mode1/2/3 eliminating switching noise in the transition. ...
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... System Reset The AK4614 should be reset once by bringing the PDN pin = “L” upon power-up. The AK4614 is powered up and the internal timing starts clocking by LRCK “↑” after exiting the power down state of reference voltage (such as VCOM) by MCLK. The AK4614 is in power-down mode until MCLK and LRCK are input. ...
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... There is a delay, 3~4/fs from PDN pin “H” to the start of initial cycle. (11) DZF pin= “L” for 10∼11/fs after PDN pin = “↑”. (12) The PDN pin must be “L” when power up the AK4614 and set to “H” after all poweres are supplied. Figure 44. Pin power-down/Pin power-up sequence example ...
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All ADCs and all DACs can be powered-down individually through the PMADC bits and PMDAC bits, when the PMVR bit “1”. ADC1-3 can be power-down individually through the PMAD3-1 bits. DAC1-6 can be power-down individually by PMDA6-1 bits. In this ...
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Reset Function When RSTN bit= “0”, the analog and digital part of ADC and the digital part of DACs are powered-down, but the internal register are not initialized. The analog outputs go to VCOM voltage regardless of the DVMPD ...
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ADC partial Power-Down Function All of the ADCs can be powered-down individually by PMAD3-1 bits. The analog section and the digital section of the ADC are in power-down mode when the PMAD3-1 bits = “0”. The analog section of ...
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... The initiation stars 2~3fs after PMDA6-1 bits are set to “1”. (6) The analog parts of DACs are initilised after exiting power down mode. (7) Although DZF detection is active at a certain channel set up though PMDA6-1 = “0”, the AK4614 stops reflecting the result of DZF detection to DZF1-2 pins. ...
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... Serial Control Interface The AK4614’s functions are controlled through registers. The registers may be written by two types of control modes. The chip address is determined by the state of the CAD0 and CAD1 inputs. The PDN pin = “L” initializes the registers to their default values. Writing “0” to the RSTN bit can initialize the internal timing circuit, but the register data will not be initialized. (1) 4-wire Serial Control Mode (I2C pin = “ ...
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... The AK4614 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4614 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 16H prior to generating a stop condition, the address counter will “ ...
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... READ Operations Set the R/W bit = “1” for the READ operation of the AK4614. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 16H prior to generating stop condition, the address counter will “ ...
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SDA SCL start condition DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S START CONDITION SDA SCL MS1025-E-00 S Figure 56. START and STOP Conditions 2 1 Figure 57. Acknowledge on the I data line change stable; ...
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... ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 [AK4614] D0 RSTN PMAD1 PMDA1 SMUTE DIV DEM10 DEM50 OVFM0 DZFM0 DIE1 DOE1 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ...
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Register Definitions Addr Register Name 00H Power Management 1 R/W Default RSTN: Internal timing reset 0: Reset. DZF1-2 pins go to “H”, but registers are not initialized. 1: Normal operation PMDAC: Power management of DAC1-6 0: Power-down 1: Normal ...
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Addr Register Name 03H Control 1 R/W Default SMUTE: Soft Mute Enable 0: Normal operation 1: All DAC outputs soft-muted ATS1-0: Digital attenuator transition time setting Initial: “00”, mode 0 DIF2-0: Audio Data Interface Modes Initial: “100”, mode 4 TDM1-0: ...
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Addr Register Name D7 05H De-emphasis1 DEM41 R/W R/W Default 0 DEMA11-10: De-emphasis response control for DAC1 data on SDTI1 Initial: “01”, OFF DEMA21-20: De-emphasis response control for DAC2 data on SDTI1 Initial: “01”, OFF DEMA31-30: De-emphasis response control for ...
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Addr Register Name D7 08H Zero Detect LOOP1 R/W R/W Default 0 DZFM3-0: Zero detect mode select Initial: “1111”, disable LOOP1-0: Loopback mode enable 00: Normal (No loop back) 01: LIN1 → LOUT1, LOUT2 RIN1 → ROUT1, ROUT2 LIN2 → ...
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Addr Register Name 0BH LOUT1 Volume Control 0CH ROUT1 Volume Control 0DH LOUT2 Volume Control 0EH ROUT2 Volume Control 0FH LOUT3 Volume Control 10H ROUT3 Volume Control 11H LOUT4 Volume Control 12H ROUT4 Volume Control 13H LOUT5 Volume Control 14H ...
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... Condition: Differential Input (DIE3-1 bit = “111”), Differential Output (DOE6-1 bit = “111111”) 4-wire Serial Control Interface (I2C pin = “L”) Master mode (M/S pin = “H”) The AK4614 has the analog Anti-Alias Filter for Differential Input. The AK4614 does not have the analog Smoothing Filter for Differential Output. LPF 61 ROUT6+ ...
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... Input (DIE3-1 bit = “000”), Single-end 2 Bus Control Interface (I2C pin = “H” Slave mode (M/S pin = “L”) The AK4614 has the analog Anti-Alias Filter for Single-Ended Input. The AK4614 has the analog Smoothing Filter for Single-Ended Output. 61 ROUT6 MUTE 62 ROUT6- OVF1 / DZF1 ...
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... ADC output data format is 2’s complement. The internal HPF removes the DC offset. The AK4614 samples the analog inputs at 128fs (@ fs=48kHz). The digital filter rejects noise above the stop band except for multiples of the sampling frequency of analog inputs. The AK4614 includes an anti-aliasing filter (RC filter) to attenuate a noise around the sampling frequency of analog inputs ...
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... External Analog Inputs Circuit shows the input buffer circuit example 1. The input level of this circuit is 4.3Vpp (AK4614: typ. ±2.15Vpp). Figure 61 Analog In 4.3Vpp 10kΩ 22μ VA 10k 0.1μ 10μ Bias 10k Figure 61. Input buffer circuit example 1 (DC coupled single-end input) shows the input buffer circuit example 2. The input level of this circuit is 4.3Vpp (AK4614: typ. ±2.15Vpp). ...
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... The output level of this circuit is 4.16Vpp (AK4614: typ. ±2.08Vpp). Figure 65 2.08Vpp AOUT- AK4614 AOUT+ 2.08Vpp Figure 65. Output buffer circuit example 1 (DC coupled differential output) shows the output buffer circuit example 2. The output level of this circuit is 4.16Vpp (AK4614: typ. ±2.08Vpp). Figure 66 2.08Vpp 20Ω A AOUT- 2200p AK4614 20Ω ...
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... AOUT- AK4614 AOUT+ Figure 67. Output buffer circuit example 3 (AC coupled single-end output) Figure 68 shows the output buffer circuit example 4. The output level of this circuit is 2.08Vpp (AK4614: typ. 2.08Vpp). AOUT- AK4614 AOUT+ Figure 68. Output buffer circuit example 4 (AC coupled single-end output) MS1025-E-00 ...
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LQFP ( Unit 1.25TYP 0.50±0.2 ■ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS1025-E-00 PACKAGE 14.0±0.2 12.0±0 0.20±0.1 0.50 0.10 Epoxy resin, Halogen (bromine, chlorine) ...
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... Date (YY/MM/DD) Revision 08/10/21 00 MS1025-E-00 MARKING AK4614VQ XXXXXXX 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4614VQ 4) Asahi Kasei Logo REVISION HISTORY Reason Page Contents First Edition - 68 - 2008/10 ...
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These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status ...