ak4650 AKM Semiconductor, Inc., ak4650 Datasheet - Page 62
ak4650
Manufacturer Part Number
ak4650
Description
16bit 6 Codec With Mic/hp/spk-amp & Tsc
Manufacturer
AKM Semiconductor, Inc.
Datasheet
1.AK4650.pdf
(86 pages)
- Current page: 62 of 86
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SYNC remains high for a total duration of 16 BITCLKs at the beginning of each audio frame. The portion of the audio
frame where SYNC is high is defined as the “Tag Phase”. The remainder of the audio frame where SYNC is low is
defined as the “Data Phase”.
Note that SDATAOUT and SDATAIN data is delayed one BITCLK because AC’97 controller causes
SYNC signal high at a rising edge of BITCLK which initiates a frame.
“Output” stream means the direction from AC’97 controller to the AK4650, and “Input” stream means the direction from
the AK4650 to AC’97 controller.
L
AC-link protocol identifies 13 slots of data per frame. The frequency of SYNC is fixed to 48kHz. Only Slot 0, which is the
Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections.
MS0502-E-01
SDATA
SDATA
SYNC
AC-Link Protocol
OUT
Slot
IN
Tag Phase
TAG
TAG
0
Command
Address
Address
Status
1
Command
Status
Data
Data
2
PCM(dac)
PCM(adc)
Left
Left
3
PCM(dac)
Right
Figure 47. AC-Link protocol
All
”0”
4
12bit ADC
Data
“0”
All
5
- 62 -
Data Phase
12bit ADC
Data
All
“0”
6
”0”
”0”
All
All
7
All
“0”
All
“0”
8
48kHz
“0”
“0”
All
All
9
10
All
“0”
All
“0”
11
“0”
“0”
All
All
[AK4650]
12bit ADC
2007/04
Data
12
All
“0”
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