ak4671 AKM Semiconductor, Inc., ak4671 Datasheet - Page 5

• Manufacturer Part Number: ak4671
• Description: Stereo Codec With Mic/rcv/hp-amp
• Manufacturer: AKM Semiconductor, Inc.

Note 1. All input pins except analog input pins (MDT, LIN1/IN1+, RIN1/IN1−, LIN2/IN2+, RIN2/IN2−, LIN3/IN3+,
MS0666-E-00
No. Pin Name
G8
H9
G9
D8
D9
A9
A8
A7
A6
A5
A4
A3
A2
E8
E9
C8
C9
B9
B8
B7
B6
B5
B4
B3
B2
C3
F8
F9
J8
SDTIA
BICKA
SYNCA
SDTOA
TVDD2
VSS2
PVDD
VCOCBT
VCOC
VCOM
MUTET
ROUT2
LOUT2
TEST
AVDD
VSS1
ROUT1
RCN
LOUT1
RCP
ROUT3
LON
LOUT3
LOP
RIN4
IN4−
LIN4
IN4+
RIN3
IN3−
LIN3
IN3+
RIN2
IN2−
LIN2
IN2+
RIN1
IN1−
LIN1
IN1+
NC
RIN3/IN3−, LIN4/IN4+, RIN4/IN4−, SAIN1, SAIN2, SAIN3) should not be left floating.
I/O pins except SDA pin (LRCK, BICK, SYNCA, BICKA, SYNCB, BICKB) should be processed appropriately.
Please refer the
should be pulled-up by a resistor externally and be connected to (DVDD+0.3)V or less voltage.
“Master Mode/Slave
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
-
-
-
-
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
Serial Data Input A Pin
Serial Data Clock A Pin
Sync Signal A Pin
Serial Data Output A Pin
Digital I/O Power Supply 2 Pin, 1.6 ∼ 3.6V
Ground 2 Pin
PLLBT Power Supply Pin, 2.2 ∼ 3.6V
Output Pin for Loop Filter of PLLBT Circuit
Output Pin for Loop Filter of PLL Circuit
Common Voltage Output Pin, 0.5 x AVDD
Mute Time Constant Control Pin
Rch Headphone-Amp Output Pin
Lch Headphone-Amp Output Pin
Test Pin
Analog Power Supply Pin, 2.2 ∼ 3.6V
Ground 1 Pin
Rch Stereo Line Output 1 Pin (RCV bit = “0”: Stereo Line Output)
Receiver-Amp Negative Output Pin (RCV bit = “1”: Receiver Output)
Lch Stereo Line Output 1 Pin (RCV bit = “0”: Stereo Line Output)
Receiver-Amp Positive Output Pin (RCV bit = “1”: Receiver Output)
Rch Stereo Line Output 3 Pin (LODIF bit = “0”: Single-ended Stereo Output)
Negative Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
Lch Stereo Line Output 3 Pin (LODIF bit = “0”: Single-ended Stereo Output)
Positive Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
Rch Analog Input 4 Pin (MDIF4 bit = “0”: Single-ended Input)
Negative Line Input 4 Pin (MDIF4 bit = “1”: Full-differential Input)
Lch Analog Input 4 Pin (MDIF4 bit = “0”: Single-ended Input)
Positive Line Input 4 Pin (MDIF4 bit = “1”: Full-differential Input)
Rch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input)
Negative Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input)
Lch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input)
Positive Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input)
Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
Negative Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
Positive Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
Negative Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
Positive Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
No Connect Pin
Connected to VSS1 pin with a capacitor for mute time constant.
This pin should be open.
No internal bonding. This pin should be open or connected to the ground.
This pin should be connected to VSS2 pin with one resistor and capacitor in series.
This pin should be connected to VSS1 pin with one resistor and capacitor in series.
Bias voltage of ADC inputs and DAC outputs.
Mode” (P.45) and
- 5 -
“PCM I/F Master Mode/Slave
Function
Mode” (P.105). SDA pin
[AK4671]
2007/10