ak4671 AKM Semiconductor, Inc., ak4671 Datasheet - Page 45

no-image

ak4671

Manufacturer Part Number
ak4671
Description
Stereo Codec With Mic/rcv/hp-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ak4671EG-L
Manufacturer:
NXP
Quantity:
8 122
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3-2 bits
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from the MCKO pin at MCKO bit
is “1” before the PLL goes to lock state after PMPLL bit = “0”
(Table
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0”
“1”. After that, the clock selected by
invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL and DACH
bits.
MS0666-E-00
PLL State
After that PMPLL bit “0”
PLL Unlock (except above case)
PLL Lock
PLL Unlock State
7).
Others
Mode
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
0
1
2
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
FS3 bit
PLL State
After that PMPLL bit “0”
PLL Unlock
PLL Lock
0
0
1
“1”
FS2 bit
0
1
x
Table 9
MCKO bit = “0”
Others
“L” Output
“L” Output
“L” Output
is output from the MCKO pin when PLL is locked. ADC and DAC output
FS1 bit
x
x
x
“1”
MCKO pin
- 45 -
MCKO bit = “0”
MCKO bit = “1”
FS0 bit
“L” Output
“L” Output
“L” Output
See
x
x
x
“1”. If MCKO bit is “0”, the MCKO pin changes to “L”
Invalid
Invalid
Table 9
(x: Don’t care, N/A: Not available)
MCKO pin
Sampling Frequency Range
12kHz < fs ≤ 24kHz
24kHz < fs ≤ 48kHz
8kHz ≤ fs ≤ 12kHz
MCKO bit = “1”
See
“L” Output
Invalid
Invalid
Output
BICK pin
N/A
Invalid
Table 10
“L” Output
1fs Output
LRCK pin
(default)
(Table
Invalid
[AK4671]
2007/10
6).

Related parts for ak4671