ak4671 AKM Semiconductor, Inc., ak4671 Datasheet - Page 154

• Manufacturer Part Number: ak4671
• Description: Stereo Codec With Mic/rcv/hp-amp
• Manufacturer: AKM Semiconductor, Inc.

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MS0666-E-00
PFMXL/R1-0 bits
(Addr:1AH&1BH, D7-0)
(Addr:0DH&0EH, D0)
(Speaker Playback: SDTI → Audio I/F → SVOLA → DATT → DACL/R → LOUT3/ROUT3 → External SPK-Amp)
Stereo Line Output
(Addr:11H, D7-D6)
DACSL/R bits
OVL/R7-0 bits
PMDAL/R bits
PML/RO3 bits
L3VL1-0 bits
(Addr:01H, D7-4)
(Addr:15H, D3-0)
(Addr:00H, D7-6)
(Addr:11H, D1-0)
(Addr:1DH, D0)
(Addr:11H, D2)
PFSEL bis
ROUT3 pin
LOUT3 pin
FS3-0 bits
LOPS3 bit
<Example>
At first, clocks should be supplied according to
(1) Set up the sampling frequency (FS3-0 bits). When the AK4671 is PLL mode, DAC and Stereo Line-Amp
(2) Set up the path of “SDTI
(3) Set up the output digital volume (Addr: 1AH and 1BH)
(4) Enter power-save mode of Stereo Line-Amp: LOPS3 bit = “0”
(5) Power-up DAC and Stereo Line-Amp: PMDAL = PMDAR = PMLO3 = PMRO3 bits = “0” → “1”
(6) Exit power-save mode of Stereo Line-Amp: LOPS3 bit = “1”
(7) Enter power-save mode of Stereo Line-Amp: LOPS3 bit: “0”
(8) Power-down DAC and Stereo Line-Amp: PMDAL = PMDAR = PMLO3 = PMRO3 bits = “1” → “0”
(9) Disable the path of “DAC
(10) Exit power-save mode of Stereo Line-Amp: LOPS3 bit = “1”
should be powered-up in consideration of PLL lock time after the sampling frequency is changed.
“0000”
Set up analog volume for Stereo Line-Amp (Addr: 11H, L3VL1-0 bits)
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
LOUT3 and ROUT3 pins rise up to VCOM voltage after PMLO3 and PMRO3 bits are changed to “1”. Rise
time is 300ms(max.) at C=1 μ F and AVDD=3.3V.
LOPS3 bit should be set to “0” after LOUT3 and ROUT3 pins rise up. Stereo Line-Amp goes to normal
operation by setting LOPS3 bit to “0”.
LOUT3 and ROUT3 pins fall down to VSS1. Fall time is 300ms(max.) at C=1 μ F and AVDD=3.3V.
LOPS3 bit should be set to “0” after LOUT3 and ROUT3 pins fall down.
0000
0000
10
18H
“0101”, DACSL = DACSR bits = “0”
(1)
(2)
(3)
(4)
DAC
(5)
>300 ms
Stereo Line-Amp”: DACSL = DACSR bits = “1”
Figure 116. Stereo Lineout Sequence
Stereo Line-Amp”: PFSEL = “0”
(6)
Normal Output
1111
0101
28H
01
“Clock Set
- 154 -
(7)
“1”
Up” sequence.
(8)
>300 ms
(9)
“1”
“0”
“0”
(10)
“1”
Example:
PLL, Master Mode
OVOLC bit = “1”(default)
LINEOUT Volume Level: −3dB
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume Level: −8dB
“1”, PFMXL1-0 = PFMXR1-0 bits =
(5) Addr:00H, Data:C1H
(1) Addr:01H, Data:F4H
(4) Addr:11H, Data:44H
(6) Addr:11H, Data:43H
(7) Addr:11H, Data:47H
(8) Addr:00H, Data:01H
(3) Addr:1AH&1BH, Data:28H
(10) Addr:11H, Data:40H
(9) Addr:0DH&0E, Data:00H
(2) Addr:11H, Data:40H
Addr:11H, Data:47H
Addr:11H, Data:44H
Addr:0DH&0EH, Data:01H
Addr:1DH, Data:01H
Addr:15H, Data:05H
Playback
“0”
[AK4671]
2007/10