ak4671 AKM Semiconductor, Inc., ak4671 Datasheet - Page 148

• Manufacturer Part Number: ak4671
• Description: Stereo Codec With Mic/rcv/hp-amp
• Manufacturer: AKM Semiconductor, Inc.

MS0666-E-00
Power Supply
PMVCM bit
(Addr:00H, D0)
(Addr:02H, D2)
(Addr:02H, D0)
2. PLL Slave Mode (MCKI pin)
PMPLL bit
MCKO pin
<Example>
MCKO bit
MCKI pin
LRCK pin
BICK pin
PDN pin
(1) After Power Up, PDN pin = “L”
(2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0”
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
(6) The normal clock is output from MCKO during this period.
(7) The invalid frequency is output from MCKO after PLL is locked.
(8) BICK and LRCK clocks should be synchronized with MCKO clock.
PLL lock time is 40ms(max.).
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
VCOM should first be powered up before the other block operates.
(1)
(2)
(3)
(4)
(5)
40msec(max)
Figure 110. Clock Set Up Sequence (2)
(6)
“H”. “L” time of 150ns or more is needed to reset the AK4671.
Input
“1”
(7)
(8)
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Output
Input
Example:
(1) Power Supply & PDN pin = “L”
Input Master Clock Select at PLL Mode: 11.2896MHz
BICK frequency at Master Mode: 64fs
Audio I/F Format: MSB justified (ADC & DAC)
MCKO: Enable
Sampling Frequency: 44.1kHz
BICK and LRCK input start
(2)Addr:03H, Data:02H
(3)Addr:00H, Data:01H
(4)Addr:02H, Data:25H
Addr:01H, Data:F4H
MCKO output start
[AK4671]
“H”
2007/10