ak4671 AKM Semiconductor, Inc., ak4671 Datasheet - Page 120

• Manufacturer Part Number: ak4671
• Description: Stereo Codec With Mic/rcv/hp-amp
• Manufacturer: AKM Semiconductor, Inc.

Addr
00H
■
MS0666-E-00
Register Definitions
PMVCM: VCOM Power Management
PMMP: MPWR pin Power Management
PMMICL: MIC-Amp Lch Power Management
PMMICR: MIC-Amp Rch Power Management
PMADL: ADC Lch Power Management
PMADR: ADC Rch Power Management
PMDAL: DAC Lch Power Management
PMDAR: DAC Rch Power Management
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless of setting of this address. In this case, register is initialized to the default value.
When all power management bits are “0”, all blocks are powered-down. The register values remain unchanged. Power
supply current is 20 μ A(typ) in this case. For fully shut down (typ. 1 μ A), PDN pin should be “L”.
When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks
must always be present.
Register Name
AD/DA Power Management
0: Power down (default)
1: Power up
0: Power down: Hi-Z (default)
1: Power up
0: Power down (default)
1: Power up
0: Power down (default)
1: Power up
0: Power down (default)
1: Power up
0: Power down (default)
1: Power up
0: Power down (default)
1: Power up
0: Power down (default)
1: Power up
(default)
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when all power management bits are “0”.
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
R/W
PMDAR
R/W
D7
0
PMDAL
R/W
D6
0
- 120 -
PMADR
R/W
D5
0
PMADL
R/W
D4
0
PMMICR
R/W
D3
0
PMMICL
R/W
D2
0
PMMP
R/W
D1
0
[AK4671]
2007/10
PMVCM
R/W
D0
0