74HCT240N,652 NXP Semiconductors, 74HCT240N,652 Datasheet - Page 9

IC INVERTER DUAL 4-INPUT 20DIP

74HCT240N,652

Manufacturer Part Number
74HCT240N,652
Description
IC INVERTER DUAL 4-INPUT 20DIP
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheet

Specifications of 74HCT240N,652

Logic Type
Inverter
Package / Case
20-DIP (0.300", 7.62mm)
Number Of Inputs
4
Number Of Circuits
2
Current - Output High, Low
6mA, 6mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Through Hole
Logic Family
74HCT
Number Of Channels Per Chip
8
Polarity
Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
125 C
Mounting Style
Through Hole
High Level Output Current
- 6 mA
Low Level Output Current
6 mA
Maximum Power Dissipation
750 mW
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
10 / 8
Output Type
3-State
Propagation Delay Time
9 ns
Logical Function
Buffer/Line Driver
Number Of Elements
2
Number Of Channels
8
Number Of Outputs
8
Operating Supply Voltage (typ)
5V
Package Type
PDIP
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Quiescent Current
8uA
Technology
CMOS
Pin Count
20
Mounting
Through Hole
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1527-5
74HCT240N
933670770652
NXP Semiconductors
Table 8.
74HC_HCT240_3
Product data sheet
Type
74HC240
74HCT240
Fig 7. 3-state enable and disable times
Measurement points are given in
V
OL
Measurement points
and V
OH
are typical voltage output drop that occur with the output load.
Input
V
0.5
1.3 V
M
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
nYn output
nYn output
nOE input
V
CC
GND
GND
Table
V
V
V
CC
OH
OL
V
I
8.
V
Output
V
0.5
1.3 V
enabled
Rev. 03 — 2 August 2007
outputs
M
M
t
t
PLZ
PHZ
V
CC
V
X
V
Y
disabled
outputs
V
0.1
0.1
74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting
X
t
PZL
t
PZH
V
V
CC
CC
V
M
V
M
001aae014
outputs
enabled
V
0.9
0.9
Y
© NXP B.V. 2007. All rights reserved.
V
V
CC
CC
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