adum5401w Analog Devices, Inc., adum5401w Datasheet - Page 15
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adum5401w
Manufacturer Part Number
adum5401w
Description
Quad-channel Isolators With Integrated Dc-to-dc Converter
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADUM5401W.pdf
(20 pages)
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APPLICATIONS INFORMATION
THEORY OF OPERATION
The dc-to-dc converter section of the ADuM5401W/ADuM5402W/
ADuM5403W works on principles that are common to most
modern power supplies. It is a secondary side controller architecture
with isolated pulse-width modulation (PWM) feedback. V
power is supplied to an oscillating circuit that switches current
into a chip-scale air core transformer. Power transferred to the
secondary side is rectified and regulated to 5 V. The secondary
(V
control signal that is sent to the primary (V
dedicated iCoupler data channel. The PWM modulates the
oscillator circuit to control the power being sent to the secondary
side. Feedback allows for significantly higher power and efficiency.
The ADuM5401W/ADuM5402W/ADuM5403W implement
undervoltage lockout (UVLO) with hysteresis on the V
input. This feature ensures that the converter does not enter
oscillation due to noisy input power or slow power-on ramp rates.
A minimum load current of 10 mA is recommended to ensure
optimum load regulation. Smaller loads can generate excess noise on
chip due to short or erratic PWM pulses. Excess noise generated
this way can cause data corruption, in some circumstances.
PCB LAYOUT
The ADuM5401W/ADuM5402W/ADuM5403W digital isolators
with 0.5 W isoPower integrated dc-to-dc converters require no
external interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins (see
Figure 20). Note that a low ESR bypass capacitor is required
between Pin 1 and Pin 2 as well as between Pin 15 and Pin 16,
as close to the chip pads as possible.
The power supply section of the ADuM5401W/ADuM5402W/
ADuM5403W uses a 180 MHz oscillator frequency to efficiently
pass power through its chip-scale transformers. In addition,
normal operation of the data section of the iCoupler introduces
switching transients on the power supply pins. Bypass capacitors
are required for several operating frequencies. Noise suppression
requires a low inductance, high frequency capacitor; ripple
suppression and proper regulation require a large value capacitor.
These are most conveniently connected between Pin 1 and Pin 2
for V
noise and reduce ripple, a parallel combination of at least two
capacitors is required. The recommended capacitor values are
0.1 μF and 10 μF for V
be used when optimum EMI emissions performance is desired.
The smaller capacitors must have a low ESR; for example, use
of an NPO ceramic capacitor is advised.
ISO
) side controller regulates the output by creating a PWM
DD1
and between Pin 15 and Pin 16 for V
DD1
and V
ISO
. A 10 nF capacitor should
DD1
ISO
) side by a
. To suppress
DD1
DD1
power
Rev. 0 | Page 15 of 20
Note that the total lead length between the ends of the low ESR
capacitor and the input power supply pin must not exceed 2 mm.
Installing the bypass capacitor with traces more than 2 mm in
length may result in data corruption. A bypass between Pin 1 and
Pin 8 and between Pin 9 and Pin 16 should also be considered
unless both common ground pins are connected together
close to the package.
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component side.
Failure to ensure this can cause voltage differentials between pins,
exceeding the absolute maximum ratings specified in Table 10,
thereby leading to latch-up and/or permanent damage.
The ADuM5401W/ADuM5402W/ADuM5403W are power
devices that dissipate about 1 W of power when fully loaded and
running at maximum speed. Because it is not possible to apply a
heat sink to an isolation device, the devices primarily depend
on heat dissipation into the PCB through the ground pins. If the
devices are used at high ambient temperatures, provide a thermal
path from the ground pins to the PCB ground plane. The board
layout in Figure 20 shows enlarged pads for Pin 8 and Pin 9. Large
diameter vias should be implemented from the pad to the ground,
and power planes should be used to reduce inductance. Multiple
vias in the thermal pads can significantly reduce temperatures
inside the chip. The dimensions of the expanded pads are left to
the discretion of the designer and the available board space.
THERMAL ANALYSIS
The ADuM5401W/ADuM5402W/ADuM5403W parts consist of
four internal die attached to a split lead frame with two die attach
paddles. For the purposes of thermal analysis, the die is treated
as a thermal unit, with the highest junction temperature reflected
in the θ
taken with the parts mounted on a JEDEC standard, 4-layer board
with fine width traces and still air. Under normal operating
conditions, the ADuM5401W/ADuM5402W/ADuM5403W
devices operate at full load across the full temperature range
without derating the output current. However, following the
recommendations in the PCB Layout section decreases thermal
resistance to the PCB, allowing increased thermal margins in
high ambient temperatures.
ADuM5401W/ADuM5402W/ADuM5403W
V
V
BYPASS < 2mm
RC
IB
IC
GND
GND
V
/V
/V
V
DD1
OUT
JA
V
OB
OC
OD
IA
from Table 5. The value of θ
1
1
Figure 20. Recommended Printed Circuit Board Layout
JA
is based on measurements
V
GND
V
V
V
V
V
GND
ISO
OA
OB
OC
ID
SEL
/V
/V
ISO
ISO
IB
IC