adum3200 Analog Devices, Inc., adum3200 Datasheet - Page 9
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adum3200
Manufacturer Part Number
adum3200
Description
Dual-channel, Digital Isolators, Enhanced System-level Esd Reliability
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADUM3200.pdf
(20 pages)
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Parameter
1
2
3
4
5
6
7
8
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total I
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
t
measured from the 50% level of the rising edge of the V
t
load within the recommended operating conditions.
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
CM
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply
current for a given data rate.
PHL
PSK
ADuM320xCR
For All Models
H
is the magnitude of the worst-case difference in t
propagation delay is measured from the 50% level of the falling edge of the V
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching,
Channel-to-Channel Matching,
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
Common-Mode Transient Immunity
Refresh Rate
Input Dynamic Supply Current,
Output Dynamic Supply Current,
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
Codirectional Channels
Opposing Directional Channels
at Logic High Output
at Logic Low Output
per Channel
per Channel
Change vs. Temperature
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
DD1
and I
DD2
supply currents as a function of data rate for ADuM3200 and ADuM3201 channel configurations.
8
8
4
3
2
7
7
5
PLH
6
– t
PHL
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
|
4
6
PHL
and/or t
Ix
signal to the 50% level of the rising edge of the V
Symbol
PW
t
PWD
t
t
t
t
|CM
|CM
f
I
I
r
DDI (D)
DDO (D)
PHL
PSK
PSKCD
PSKOD
R
/t
PLH
, t
f
H
L
|
|
PLH
that is measured between units at the same operating temperature, supply voltages, and output
Rev. 0 | Page 9 of 20
Min
25
20
25
25
Ix
signal to the 50% level of the falling edge of the V
Typ
20
50
5
3.0
2.5
35
35
1.2
1.1
0.19
0.10
0.03
0.05
O
> 0.8 V
Max
40
50
3
15
3
15
DD2
Ox
. CM
signal.
L
is the maximum common-mode voltage slew rate
mA/Mbps
Unit
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
ns
kV/µs
kV/µs
Mbps
Mbps
mA/Mbps
mA/Mbps
mA/Mbps
ADuM3200/ADuM3201
Ox
Test Conditions
C
C
C
C
C
C
C
C
C
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
signal. t
L
L
L
L
L
L
L
L
L
L
Ix
Ix
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= V
= 0 V, V
DD1
PLH
, V
propagation delay is
CM
DD2
= 1000 V,
, V
CM
= 1000 V,