wm8805 Wolfson Microelectronics plc, wm8805 Datasheet - Page 25

• Manufacturer Part Number: wm8805
• Description: 8 1 Digital Interface Transceiver With Pll
• Manufacturer: Wolfson Microelectronics plc

Table 23 User Mode PLL Configuration Examples
w
Production Data
(MHz)
OSC
CLK
12
12
12
12
12
24
24
24
24
24
27
27
27
27
SCALE
PRE-
0
0
0
0
0
1
1
1
1
1
1
1
1
1
(MHz)
13.5
13.5
13.5
13.5
12
12
12
12
12
12
12
12
12
12
F
1
When considering settings not shown in this table, the key configuration parameters which must be
selected for optimum operation are:
PLL INTEGER AND FRACTIONAL CONTROL MODES
The PLL can be operated in either fractional or integer control modes. In PLL User Mode, it is
recommended that the PLL should be operated in fractional control mode at all times. When
the S/PDIF receiver is enabled, the PLL must be operated in fractional control mode.
Table 24 PLL Fractional/Integer Mode Select
MASTER CLOCK (MCLK)
The master clock (MCLK) signal is used to supply reference clock signals to the following circuit
blocks:
The master clock (MCLK) pin can be configured as either a clock input or output depending on the
digital audio interface mode as shown in Table 25.
REGISTER
ADDRESS
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
98.304
98.304
98.304
98.304
98.304
98.304
98.304
(MHz)
•
•
PLL5
•
•
•
07h
R7
F
2
The Digital Audio Interface
The S/PDIF Transmitter
90MHz ≤ f
5 ≤ PLL_N ≤ 13
OSCCLOCK = 10 to 14.4MHz or 16.28 to 27MHz
7.5264
7.5264
7.5264
7.5264
7.5264
7.2818
7.2818
6.6901
6.6901
8.192
8.192
8.192
8.192
8.192
BIT
R
2
2
≤ 100MHz
PLL_N
(Hex)
8
8
8
8
8
7
7
7
7
7
7
7
6
6
FRACEN
LABEL
2C2B24
2C2B24
21B089
21B089
21B089
21B089
21B089
1208A5
1208A5
C49BA
C49BA
C49BA
C49BA
C49BA
PLL_K
(Hex)
DEFAULT
MODE
FREQ
[1:0]
00
10
10
10
10
01
10
10
10
10
10
10
10
10
1
MCLK
DIV
Integer/Fractional PLL Mode
Select
0 = Integer PLL (PLL_N value used,
PLL_K value ignored)
1 = Fractional PLL (both PLL_N and
PLL_K values used)
Note: FRACEN must be set to
enable the fractional PLL when
using S/PDIF Receive Mode.
1
0
1
0
1
0
0
1
0
1
0
1
0
1
22.5792
11.2896
11.2896
11.2896
24.576
12.288
12.288
5.6448
5.6448
12.288
5.6448
MCLK
6.144
6.144
6.144
(MHz)
DESCRIPTION
PD, Rev 4.5, March 2009
CLKOUT
[1:0]
DIV
01
00
01
10
11
00
00
01
10
11
01
10
01
10
WM8805
45.1584
22.5792
11.2896
11.2896
49.152
24.576
12.288
5.6448
2.8224
12.288
5.6448
(MHz)
6.144
3.072
6.144
25
CLK
OUT