wm8982gefl-v Wolfson Microelectronics plc, wm8982gefl-v Datasheet - Page 78

• Manufacturer Part Number: wm8982gefl-v
• Description: Mono Codec With Speaker Driver And Video Buffer
• Manufacturer: Wolfson Microelectronics plc

WM8982
Figure 51 DAC Power Up and Down Sequence (not to scale)
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Notes:
The analogue input pin charge time, t
dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD
power supply rise time.
The analogue input pin discharge time, t
capacitor discharge time. The time, t
input but will vary dependent upon the value of input coupling capacitor.
While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system noise
but no significant digital output will be present.
The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for normal
ADC operation.
ADCDAT data output delay from power up - with power supplies starting from 0V - is determined
primarily by the VMID charge time. ADC initialisation and power management bits may be set
immediately after POR is released; VMID charge time will be significantly longer and will dictate
when the device is stabilised for analogue input.
ADCDAT data output delay at power up from device standby (power supplies already applied) is
determined by ADC initialisation time, 2/fs.
midrail_on,
midrail_off
midrail_off,
is determined by the VMID pin charge time. This time is
, is measured using a 1µF capacitor on the analogue
is determined by the analogue input coupling
PP, Rev 3.2, September 2008
Pre-Production
78