wm8982gefl-v Wolfson Microelectronics plc, wm8982gefl-v Datasheet - Page 14
wm8982gefl-v
Manufacturer Part Number
wm8982gefl-v
Description
Mono Codec With Speaker Driver And Video Buffer
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8982GEFL-V.pdf
(108 pages)
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WM8982
CONTROL INTERFACE TIMING – 3-WIRE MODE
w
Test Conditions
DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T
MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
SYMBOL
t
t
t
t
t
t
t
t
t
DHO
SCS
SCY
SCL
SCH
DSU
CSL
CSH
CSS
t
ps
MIN
200
80
80
80
40
40
40
40
40
0
A
=+25
TYP
PP, Rev 3.2, September 2008
o
C, Slave Mode, fs=48kHz,
MAX
5
Pre-Production
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
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