wm8952 Wolfson Microelectronics plc, wm8952 Datasheet - Page 45

• Manufacturer Part Number: wm8952
• Description: Mono Adc With Microphone Pre-amplifier
• Manufacturer: Wolfson Microelectronics plc

Pre Production
w
EXAMPLE:
The PLL performs best when f
are shown in Table 35.
Table 35 PLL Frequency Examples
PLL input clock (f
R should be chosen to ensure 5 < N < 13. There is a fixed divide by 4 in the PLL and a selectable
divider (MCLKDIV[3:0]) after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f
So N[3:0] will be 8h and K[23:0] will be 3126E9h to produce the desired 98.304MHz clock.
(MHz)
19.68
19.68
MCLK
14.4
14.4
19.2
19.2
19.8
19.8
12
12
13
13
24
24
26
26
27
27
R = 98.304 / 12 = 8.192
N = int R = 8
K = int (2
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
DESIRED
OUTPUT
(MHz)
1
) is 12MHz and the required clock (SYSCLK) is 12.288MHz.
24
x (8.192 – 8)) = 3221225 = 3126E9h
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
(MHz)
F2
2
is around 90MHz. Its stability peaks at N=8. Some example settings
PRESCALE
DIVIDE
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
= 4 * 2 * 12.288MHz = 98.304MHz.
POSTSCALE
(MCLKDIV)
DIVIDE
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
6.947446
7.561846
6.826667
9.178537
9.990243
9.122909
9.929697
6.947446
7.561846
6.690133
7.281778
7.5264
7.5264
8.192
6.272
9.408
10.24
8.192
PP, Rev 3.0, December 2008
R
(Hex)
A
7
8
6
7
6
6
9
9
9
9
9
7
8
6
7
6
7
N
WM8952
BOAC93
45A1CA
D3A06E
F28BD4
3D70A3
2DB492
FD809F
EE009E
F28BD4
86C226
8FD525
1F76F8
86C226
8FD525
3126E9
6872B0
3126E9
482296
(Hex)
K
45