wm8952 Wolfson Microelectronics plc, wm8952 Datasheet - Page 44

• Manufacturer Part Number: wm8952
• Description: Mono Adc With Microphone Pre-amplifier
• Manufacturer: Wolfson Microelectronics plc

WM8952
w
Table 33 PLL Frequency Ratio Control
INTEGER N DIVISION
Table 34 PLL Modes of Operation (Integer N mode)
FRACTIONAL K MODE
The PLL frequency ratio R = f
N controls the ratio of the division, and K the fractional part.
The PLL output then passes through a fixed divide by 4, and can also be further divided by
MCLKDIV[3:0] (see Figure 24). The divided clock (SYSCLK) can be used to clock the WM8952
DSP core.
The integer division ratio (N) is determined by N[3:0] and must be in the range 5 to 12 .
If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low
power operation.
The Fractional K bits provides K[23:0] provide finer divide resolution for the PLL frequency ratio (up
to 1/2
division X, the fractional division K[23:0] and the integer division N[3:0] is:
where 0 < (R – N) < 1 and K is rounded to the nearest whole number.
REGISTER
ADDRESS
R36
PLL N value
R37
PLL K value 1
R38
PLL K Value 2
R39
PLL K Value 3
INPUT CLOCK
11.2896MHz
12.2880MHz
24
(F
). If these are used then FRAC_EN must be set. The relationship between the required
1
N = int R
K = int (2
K = 2
)
24
( R – N)
7
6
5:4
3:0
5:0
8:0
8:0
24
BIT
(R - N))
DESIRED PLL
90.3168MHz
98.3040MHz
OUTPUT (F
PLL_POWERDOWN
FRACEN
PLLPRESCALE
PLLN
PLLK [23:18]
PLLK [17:9]
PLLK [8:0]
2
/f
1
LABEL
(see Table 33) can be set using the register bits PLLK and PLLN:
2
)
REQUIRED (R)
DIVISION
0
1
00
1000
0Ch
093h
0E9h
DEFAULT
8
8
PLL POWER
0=ON
1=OFF
0=Disabled (Lower Power)
1=Enabled
00 = MCLK input multiplied by 2
(default)
01 = MCLK input not divided
10 = Divide MCLK by 2 before input to
PLL
11 = Divide MCLK by 4 before input to
PLL
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
Fractional Divide within the PLL
FRACTIONAL
DIVISION (K)
0
0
PP, Rev 3.0, December 2008
DESCRIPTION
DIVISION (N)
INTEGER
8
8
Pre Production
SDM
0
0
44