ak4373 ETC-unknow, ak4373 Datasheet - Page 31

• Manufacturer Part Number: ak4373
• Description: Low Power Stereo Dac With Hp/spk-amp
• Manufacturer: ETC-unknow

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1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, the LRCK and BICK pins go to “L” and irregular frequency clock is output from the MCKO pin at MCKO
bit is “1” before the PLL goes to lock state after PMPLL bit = “0”
(Table
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, the BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0”
“1”. After that, the clock selected by
when the PLL is unlocked. The output signal should be muted by writing “0” to DACH and DACS bits.
MS0991-E-00
PLL State
After that PMPLL bit “0”
PLL Unlock (except above case)
PLL Lock
PLL Unlock State
8).
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
After that PMPLL bit “0”
PLL Unlock
PLL Lock
“1”
Table 10
MCKO bit = “0”
“L” Output
“L” Output
“L” Output
is output from the MCKO pin when PLL is locked. DAC output invalid data
“1”
MCKO pin
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MCKO bit = “0”
MCKO bit = “1”
“L” Output
“L” Output
“L” Output
See
Invalid
Invalid
Table 10
“1”. If MCKO bit is “0”, the MCKO pin goes to “L”
MCKO pin
MCKO bit = “1”
See
“L” Output
Invalid
Invalid
Output
BICK pin
Invalid
Table 11
“L” Output
LRCK pin
1fs Output
Invalid
[AK4373]
2008/09