km416v4004b Samsung Semiconductor, Inc., km416v4004b Datasheet - Page 8

• Manufacturer Part Number: km416v4004b
• Description: 4m X 16bit Cmos Dynamic Ram With Extended Data Out
• Manufacturer: Samsung Semiconductor, Inc.

KM416V4004B, KM416V4104B
NOTES
KM416V40(1)04B Truth Table
10.
11.
12.
13.
14.
15.
RAS
1.
2.
3.
4.
5.
6.
7.
8.
9.
H
L
L
L
L
L
L
L
L
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
V
V
Measured with a load equivalent to 1 TTL load and 100pF.
Operation within the
If
Assumes that
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
t
teristics only. If
tion of the cycle. If
data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of
the data out is indeterminate.
Either
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
Operation within the
If
These specifications are applied in the test mode.
In test mode read cycle, the value of
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
t
t
t
WCS
ASC
CP
CWD
IH
IH
t
t
RCD
RAD
(min) and V
(min) and V
is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
,
,
t
is referenced to the later CAS falling edge at word read-modify-write cycle.
t
CAH
t
RWD
is greater than the specified
is greater than the specified
RCH
LCAS
are referenced to the earlier CAS falling edge.
,
or
X
H
H
H
L
L
L
L
L
t
CWD
t
t
IL
RCD
RRH
IL
t
WCS
(max) and are assumed to be 2ns for all inputs.
(max) are reference levels for measuring timing of input signals. Transition times are measured between
and
t
CWD
must be satisfied for a read cycle.
t
t
RCD
t
RCD
t
RAD
t
WCS
AWD
UCAS
(max).
t
(max) limit insures that
(max) limit insures that
CWD
X
H
H
H
L
L
L
L
L
(min), the cycle is an early write cycle and the data output will remain high impedance for the dura-
are non restrictive operating parameters. They are included in the data sheet as electrical charac-
(min),
t
t
t
RAD
RCD
RWD
t
RAC
(max) limit, then access time is controlled by
(max) limit, then access time is controlled exclusively by
W
X
X
H
H
H
H
L
L
L
t
RWD
,
t
AA
(min) and
,
t
t
t
RAC
RAC
CAC
(max) can be met.
(max) can be met,
OE
is delayed by 2ns to 5ns for the specified values. These parameters
X
X
H
H
H
H
L
L
L
t
AWD
t
AWD
DQ0 - DQ7
(min), then the cycle is a read-modify-write cycle and the
DQ-OUT
DQ-OUT
DQ-IN
DQ-IN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
t
t
RCD
RAD
-
(max) is specified as a reference point only.
(max) is specified as a reference point only.
t
AA
.
DQ8-DQ15
DQ-OUT
DQ-OUT
DQ-IN
DQ-IN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
t
CAC
CMOS DRAM
.
Word Read
Word Write
Byte Read
Byte Read
Byte Write
Byte Write
Standby
Refresh
STATE
oh
-
or V
ol
.