mc9s12xs128 Freescale Semiconductor, Inc, mc9s12xs128 Datasheet - Page 163

• Manufacturer Part Number: mc9s12xs128
• Description: Hcs12 Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4.4.3
If the XGATE module is implemented on the device, the XINT module is also used to process all exception
requests to be serviced by the XGATE module. The overall priority level of those exceptions is discussed
in the subsections below.
4.4.3.1
An interrupt request channel is configured to be handled by the XGATE module, if the RQST bit of the
associated configuration register is set to 1 (please refer to
Configuration Data Registers
channel becomes the XGATE priority which will be used to determine the highest priority XGATE request
to be serviced next by the XGATE module. Additionally, XGATE interrupts may be raised by the XGATE
module by setting one or more of the XGATE channel interrupt flags (by using the SIF instruction). This
will result in an CPU interrupt with vector address vector base + (2 * channel ID number), where the
channel ID number corresponds to the highest set channel interrupt flag, if the XGIE and channel RQST
bits are set.
The shared interrupt priority for the XGATE interrupt requests is taken from the XGATE interrupt priority
configuration register (please refer to
(INT_XGPRIO)”). If more than one XGATE interrupt request channel becomes active at the same time,
the channel with the highest vector address wins the prioritization.
4.4.4
The XINT module contains priority decoders to determine the priority for all interrupt requests pending
for the respective target.
There are two priority decoders, one for each interrupt request target, CPU or XGATE. The function of
both priority decoders is basically the same with one exception: the priority decoder for the XGATE
module does not take the current XGATE thread processing level into account. Instead, XGATE requests
are handed to the XGATE module including a 1-bit priority identifier. The XGATE module uses this
additional information to decide if the new request can interrupt a currently running thread. The 1-bit
priority identifier corresponds to the most significant bit of the priority level configuration of the requesting
channel. This means that XGATE requests with priority levels 4, 5, 6 or 7 can interrupt running XGATE
threads with priority levels 1, 2 and 3.
A CPU interrupt vector is not supplied until the CPU requests it. Therefore, it is possible that a higher
priority interrupt request could override the original exception which caused the CPU to request the vector.
In this case, the CPU will receive the highest priority vector and the system will process this exception
instead of the original request.
If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive
after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the
CPU will default to that of the spurious interrupt vector.
Freescale Semiconductor
XGATE Requests
Priority Decoders
XGATE Request Prioritization
(INT_CFDATA0–7)”). The priority level configuration (PRIOLVL) for this
S12XS Family Reference Manual, Rev. 1.10
Section 4.3.2.2, “XGATE Interrupt Priority Configuration Register
Section 4.3.2.4, “Interrupt Request
Interrupt (S12XINTV2)
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