lpc2478fet208 NXP Semiconductors, lpc2478fet208 Datasheet - Page 34

• Manufacturer Part Number: lpc2478fet208
• Description: Single-chip 16-bit/32-bit Micro; 512 Kb Flash, Ethernet, Can, Lcd, Usb 2.0 Device/host/otg, External Memory Interface Semiconductors
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2478_1
Preliminary data sheet
7.11.1 Features
The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access
the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic
in the LPC2478 takes place on a different AHB subsystem, effectively separating Ethernet
activity from the rest of the system. The Ethernet DMA can also access off-chip memory
via the EMC, as well as the SRAM located on another AHB. However, using memory
other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet access to
memory and increase the loading of its AHB.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Media
Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media
Independent Interface Management (MIIM) serial bus.
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Ethernet standards support:
– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support.
Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.
Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic Frame Check Sequence (FCS) insertion with Circular
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
Physical interface:
– Attachment of external PHY chip through standard MII or RMII interface.
– PHY register access is available via the MIIM interface.
100 Base-FX, and 100 Base-T4.
pressure.
Redundancy Check (CRC) for transmit.
receive filters or a magic frame detection filter.
Rev. 01 — 6 July 2007
Fast communication chip
LPC2478
© NXP B.V. 2007. All rights reserved.
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