tc9447f TOSHIBA Semiconductor CORPORATION, tc9447f Datasheet
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tc9447f
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tc9447f Summary of contents
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... TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic Single-Chip Audio Digital Signal Processor The TC9447F is a single-chip audio digital signal processor incorporating an AD/DA converter. The built-in program memory (ROM) can contain a range of application programs for concert hall acoustic field simulation, for digital filters such as equalizers, and for dynamic range control ...
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... Block Diagram 3 TC9447F 2002-02-05 ...
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... Test pin (leave open) 54 CKS I Master clock switching pin 55 STEP0 I Execution step switching pin 0 56 STEP1 I Execution step switching pin 1 57 RST I Reset pin Function Pulled-down resistor (with on/off switching function) Push-pull output Schmitt input Schmitt input Schmitt input Schmitt input 4 TC9447F Remarks 2002-02-05 ...
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... VDX Power pin for oscillator circuit Function 2 C bus selected bus selected bus switching pin 5 TC9447F Remarks Schmitt input Schmitt input Schmitt input Schmitt input Schmitt input Schmitt input Push-pull output Schmitt input Schmitt input Schmitt input ...
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... MCK MCKE STEP1 0 don't care 256 Source Oscillation Frequency 512 fs 768 fs For testing 6 TC9447F CKO1 Fixed to L (initial value fs2 0 fs4 1 1 fs8 0 fs16 0 1 fs32 0 fs64 1/2 ECKI MCK ...
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... Setting CKS = L enables oscillation. Setting CKS = H pulls down XI/XO using the internal resistor Function De-Emphasis Settings Mode (I Chip select (Can be fixed to L) MCU data input/output Fixed to L output Fixed to HZ Operation Start Address 000h 001h 002h 003h 7 TC9447F mode) 2002-02-05 ...
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... When the CS signal is Low, control from the microcontroller is enabled. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC9447F loads the IFDI data on the IFCK signal rising edge. When the IFCK and IFDI signals are don't care. ...
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... Setting RAM (ACMP mode) In ACMP mode, the TC9447F does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must first be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. ...
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... There are two further modes: a mode where the data bus or pointer (s) is monitored at a preset program counter (PC) and a mode where a loop counter (LC) is added to monitor conditions in addition to the PC. After the command is issued, when the TC9447F loads data to the IFDO register (IFDOR), the IFOK pin signal is set to Low (see (1) above). ...
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... When the CS signal is Low, control from the microcontroller is enabled. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC9447F loads the IFDI data on the IFCK signal rising edge. When the IFCK and IFDI signals are don't care. ...
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... Setting RAM (ACMP mode) In ACMP mode, the TC9447F does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must first be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. ...
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... There are two further modes: a mode where the data bus or pointer (s) is monitored at a preset program counter (PC) and a mode where a loop counter (LC) is added to monitor conditions in addition to the PC. After the command is issued, when the TC9447F loads data to the IFDO register (IFDOR), the IFOK pin signal is set to Low (see (1) above). ...
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... mode, the CS signal can be used fixed to L. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC9447F loads the IFDI data on the IFCK signal rising edge. When the IFCK and IFDI signals are don't care. (3-1) Setting registers The registers are set by command data using the IFDI signal ...
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... There are two further modes: a mode where the data bus or pointer (s) is monitored at a preset program counter (PC) and a mode where a loop counter (LC) is added to monitor conditions in addition to the PC. First, issue the monitoring command, which has no data. When the TC9447F loads data to the IFDO register (IFDOR), the IFOK pin signal is set to Low (see (1) above). 2 Next, the I C read command (ID = 33h) is issued, then when the IFCK signal is sent, the data are output on the IFCK signal falling edge starting from the MSB ...
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... When using a command to control the DF block mute on/off (CMD: 36h, bit 5), the mute end flag is output from the IFOK pin after the mute operation completes. Example: Note 1: At power on, the IFOK pin output is undefined. When the CS signal goes Low, the IFOK signal goes High. 16 TC9447F 2002-02-05 ...
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... CP monitor OFP monitor DP monitor AR monitor CRP monitor SR monitor 17 TC9447F Transfer Sync With/Async to Sync Signal Async Async Async Async Sync (Note 2) Sync (RUN)/Async (STOP) Sync (RUN)/Async (STOP) Async Sync (RUN)/Async (STOP) Async ...
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... ELRI pin 3 ELRO pin 0 Fixed to L (initial value) 1 fs2 2 fs4 3 fs8 4 fs16 5 fs32 6 fs64 7 Outputs XI or ECKI clock divided Fixed to L (initial value) 1 fs2 2 fs4 3 fs8 4 fs16 5 fs32 6 fs64 7 fs128 18 TC9447F CKOS1 CKOS0 CKOS0 CKOS0 2002-02-05 ...
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... ATTS4 ATTS3 ATTS2 ATTS1 ATTS0 Value Operation 00h 00h 0dB, 01h = í1dB, 02h = í2dB, , 15h~1Fh = í ~ (Initial value = 1Fh=Ù) 1Fh 00h 00h 0dB, 01h = í1dB, 02h = í2dB, , 15h~1Fh = í ~ (Initial value = 1Fh = í) 1Fh 19 TC9447F 2002-02-05 ...
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... Pads from the beginning (initial value) 1 Pads from the end format 3 20 TC9447F OBCS OBCS OFMT OFMT 2002-02-05 ...
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... Operation 000h Set sequential RAM. ~ Enable a sequential write to RAM. 3FFh Value Operation 0000h Set CRAM. ~ Enable a sequential write to RAM. FFFFh 21 TC9447F SO- OMUTE OMUTE MUTE ...
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... Value Operation 0000h ~ Set OFRAM in ACMP mode. FFFFh Value Operation 0 IFFn = 0 (initial value) 1 IFFn = 1 22 TC9447F IFF2 IFF1 ...
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... Compares with LC1 value. 0 After a match, does not change the value to be compared with the LC. After a match, automatically decrements by 1 the value compared with the LC. 00h ~ Set the value to be compared with the LC. FFh 23 TC9447F mode. ...
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... Does not use table. 1 Uses 2-k word area as the table (initial value). 0 One access/6 cycles (initial value) 1 One access/4 cycles Value Operation 0 Does not initialize. 1 Initializes (after initialization, automatically set to 0). 24 TC9447F 2002-02-05 ...
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... Operation Reads BP on the condition CMD: 4Bh, 4Ch Operation Reads delay RAM address on the condition CMD: 4Bh, 4Ch. 25 TC9447F OFP OFP OFP OFP OFP OFP ...
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... Operation Reads CRP on the condition CMD: 4Bh, 4Ch LRF GF3 GF2 GF1 GF0 Operation Reads SR on the condition CMD: 4Bh, 4Ch. 26 TC9447F CRP CRP CRP CRP CRP CRP V1F V0F ZF SF ...
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... Self-boot function description (1) Self-boot function The TC9447F supports a self-boot function for setting coefficients and offsets. As Figure 1 shows, the data are set via the microcontroller interface circuit. First saving the data to be set via the microcontroller in the self-boot ROM (SBROM) allows various modes to be set later ...
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... The boot operation when set from the microcontroller is the same as the self-boot operation at reset except that the boot operation can start from any address. Wait Period Boot Time (Maximum) 64.0 ms 32.0 ms 46.4 ms 23.2 ms 42.7 ms 21.3 ms and start address Start Address 0 000h 1 001h 0 002h 1 003h 28 TC9447F 2002-02-05 ...
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... Table 4 Differences depending on operating mode Parameter Boot Mode at Reset Boot wait period Boot start address Select from 000h to 003h Boot pin (4) Programming examples Boot Mode Set from Microcontroller Yes No Any address specified from microcontroller “H” level Don't care 30 TC9447F 2002-02-05 ...
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... Code format example The following shows the format for storing data in SBROM. 31 TC9447F 2002-02-05 ...
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... IFDI terminal is not transmitted to a microcomputer. Therefore, the acknowledgement signal of the last of IFDI signal should repeal at the time of reset command transmission. The timing at the time of reset command transmission is shown if Figure 4. Figure 4 Timing at the time of command transmission 2 C bus mode. 32 TC9447F 2002-02-05 ...
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... Therefore, IFDI terminal will be in the state of H level, and operation conditions may not be performed normally. The timing at the time of self boot command transmission is shown if Figure 5. Figure 5 Timing at the time of self boot command transmission 2 C bus mode but in the standard transmitting mode at the time of 33 TC9447F 2 C bus and 2002-02-05 ...
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... Test Condition Circuit V IH2 V IL2 I IH2 IL2 IN V TC9447F = DAS Min Typ. Max Unit 4.5 5.0 5. MHz 12 33.8 34 135 140 mA Min Typ. Max Unit 3.5 V ...
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... Test Condition Circuit í2 (Note 6) 2 í4 (Note 7) 4 4 (Note 8) TC9447F Min Typ. Max Unit 4.5 V 0.5 4.5 V 0.5 0.5 V ±10 µA 2002-02-05 ...
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... MHz 20 kHz, When using X'tal oscillator 33.8688 MHz A-Weight, When using X'tal CT d oscillator at 33.8688 MHz (Note 12) A-Weight, When using X'tal DR d oscillator at 33.8688 MHz (Note 12) 38 TC9447F Min Typ. Max Unit 1.13 1.20 Vrms (Note 9) (Note 9) 27.0 ...
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... LOH L t DO1 L t DO2 L EBCO L EBOH L EBOL L 39 TC9447F Min Typ. Max Unit 29 ns 14.5 ns 14.5 ns Min Typ. Max Unit 10 ms 1.0 µs Min Typ. ...
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... L 400 pF L 400 pF L 400 pF L 400 pF L 400 pF L 400 TC9447F Min Typ. Max Unit 1.0 µs 0.5 µs 0.5 µs 0.5 µs 0.5 µs 1.0 ...
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... AC Characteristics Test Points 1. Clock pins (XI, ECKI) 2. Reset 3. Timing output 4. Audio serial interface (ELRI, EBCI, DIN, ELRO, EBCO, DOUT) 41 TC9447F 2002-02-05 ...
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... Microcontroller interface Purchase of TOSHIBA I C components conveys a license under the Philips I 2 components system, provided that the system conforms to the I defined by Philips IFCK, IFDI, IFDO, ACK ) 2 C mode (IFCK, IFDI TC9447F 2 C Patent Right to use these C Standard Specification as 2002-02-05 ...
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... Package Dimensions Weight: 1.57 g (typ.) 43 TC9447F 2002-02-05 ...
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... TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 44 TC9447F 000707EBA 2002-02-05 ...