ncp5425 ON Semiconductor, ncp5425 Datasheet
ncp5425
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ncp5425 Summary of contents
Page 1
... NFET buck regulators utilizing a feed forward voltage mode control method. The NCP5425 can run from a single supply ranging from 4 and support a single two phase or dual single phase outputs. When used as a dual output controller, the second output tracks voltage transients from the first. Power blanking for low noise applications is supported as well as independent cycle− ...
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... C6 0 NTD60N02R NTD110N02RT4 1 680 mF1 R3 0 Figure 1. Application Diagram, 3 1.5 V/10 A and 1.8 V/5.0 A Converter NCP5425 C10 C11 GATE(H)1 GATE(H GATE(L)1 GATE(L IS−2 IS REF2 8 IS−1 ...
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... GATE(L)2 Low−Side FET Driver for , IS+1, IS+2 Positive Current Sense for IS−1, IS−2 Negative Current Sense for GND BST Power Input for GATE(H)1 MODE Dual or Single Output Select NCP5425 Rating Pin Name V MAX IC Power Input 16 V 4.0 V Channel 6.0 V Channel 5 ...
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... GATE(H) to GATE(L) Delay GATE(L) to GATE(H) Delay GATE(H)1(2) and GATE(L)1(2) Pull−Down PWM COMPARATOR Propagation Delay PWM Comparator Offset Artificial Ramp Minimum Pulse Width 2. Guaranteed by design, not 100% tested in production. NCP5425 (0°C < T < 125° 30 OSC COMP1,2 = 1.0 nF; unless otherwise specified.) Test Condition ...
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... OVC Comparator Offset Voltage IS+1(2) Bias Current IS−1(2) Bias Current OVC Common Mode Range SUPPLY CURRENTS V Current CC BST Current UNDERVOLTAGE LOCKOUT Start Threshold Stop Threshold Hysteresis NCP5425 < 125° 30 OSC = C = 1.0 nF; unless otherwise specified.) GATE(L)1,2 Test Condition R = 61.9 k; Measure GATE(H)1 OSC R = 30.9 k ...
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... A resistor from this pin to ground sets switching frequency. OSC 18 V Input Power supply pin. Power input for GATE(L)1 and GATE(L)2 pins GATE(L)2 Low Side Synchronous FET driver pin for the channel 2 FET. 20 GATE(H)2 High Side Switch FET driver pin for the channel 2 FET. NCP5425 Description http://onsemi.com 6 ...
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... REFERENCE AND BIAS 0.8 V 3.1 V − V FB1 + 0.8 V EA1 + − COMP1 − V UVLO − 4.2 V 4.0 V 3.1 V − V FB2 + V REF2 EA2 COMP2 NCP5425 RAMP1 high to activate) RAMP1 + 0.3 V CLK1 − PWM + COMP1 + − − COMP1 CLAMP REFERENCE UVLO RAMP2 + 0.3 V CLK2 − PWM + COMP2 + − − 3.1 V 3.1 V 3.1 V ...
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... APPLICATIONS INFORMATION Theory of Operation The NCP5425 is a very versatile buck controller using control method. It can be configured as • Dual output Buck Controller. • Two phase Buck Controller with current limit. • Two phase Buck Controller with input power ratio and current limit. ...
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... LOAD (nF) Figure 5. Average Rise and Fall Times NCP5425 Transient Response The 200 ns reaction time of the control loop provides fast transient response to any variations in input voltage or output current. Pulse−by−pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required ...
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... Current Sharing When used in a two separate input to a single output mode, the NCP5425 dual controller can provide input power sharing in either of two ways: • A preset ratio. For example, Channel 1 could provide 70% of the load current, and Channel 2, the remaining 30%. Practical ratios for Channel 1/Channel 2 contribution to total load current range from 50%− ...
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... R3 Output (8C) Figure 8. Inductor Current Sensing − Circuit Configurations NCP5425 current sense signal will have the same wave shape as the inductor current and the voltage signal on C1 will represent the instantaneous value of inductor current. The voltage across C1 can be used as though it were a sense resistor with the same value as the inductor’ ...
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... RS flip flop. This terminates the PWM pulse for the cycle and limits the energy delivered to the load. One advantage of this current limiting scheme is that the NCP5425 will limit large transient currents yet resume normal operation on the following cycle. A second benefit of limiting the PWM pulse width is input power sharing application, one controller can be current limiting while the other supplies the remaining load current ...
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... Assume the desired V = 1.2 V, and the tolerable error OUT due to input bias current is 0.2 (0.2)(0. − 1 1.6 K ((1.2 0. 1.6 K 0.5 + 3.2 K NCP5425 Calculating Duty Cycle The duty cycle of a buck converter (including parasitic losses) is given by the formula: Duty Cycle + D + where buck regulator output voltage; ...
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... output voltage. OUT Rearranging, we have: DV OUT ESR MAX + DI L NCP5425 The number of output capacitors is determined by: where: ESR CAP The designer must also verify that the inductor value yields reasonable inductor peak and valley currents (the inductor current is a triangular waveform): ...
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... MAX The designer must select the LC filter pole frequency such that a minimum attenuation is obtained at the regulator switching frequency. The LC filter is a NCP5425 double−pole network with a slope of −2.0, a roll−off rate of −40 dB/decade, and a corner frequency given by: where input inductor; ...
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... FET junction−to−ambient thermal qJA resistance. http://onsemi.com 16 R DS(ON OUT ( DS(ON) I LOAD non−overlap time f SW GATE(H)−to−GA TE(L) delay (from NCP5425 data sheet Electrical Characteristics section); = Synchronous (lower) FET total losses; R qJA ] = total synchronous (lower) FET losses; ...
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... Control IC Power Dissipation The power dissipation of the IC varies with the MOSFETs used, VCC, and the NCP5425 operating frequency. The average MOSFET gate charge current typically dominates the control IC power dissipation, and is given by: P CONTROL(IC CC1 V CC1 ) I BST V BST ) P GATE(H GATE(L GATE(H GATE(L)2 ...
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... Calculate the current sense resistor network (2 resistors) for the controller with the greater current share. In the two examples that follow, the inductor sense resistors are designated R1, R2, and R3, as depicted in Figures 12 and 13. NCP5425 Master Switch Node Figure 12 ...
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... Low Pass Filter Configuring a Dual Output Application To configure the NCP5425 for a dual output application: • The Mode pin must be grounded • An external voltage reference must be provided for Controller 2, via the Vref2 pin http://onsemi.com (R2 * R3) (R2 ) R3) ...
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... In applications where the internal slope compensation is insufficient, the performance of the NCP5425−based regulator can be improved through the addition of a fixed amount of external slope compensation at the output of the PWM Error Amplifier (the COMP pin) during the regulator off− ...
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... LAYOUT GUIDELINES When laying out a buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the NCP5425. 1. Rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns. 2. Keep high currents out of sensitive ground connections ...
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... G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP5425/D MAX _ 8 ...