is43r32800b Integrated Silicon Solution, Inc., is43r32800b Datasheet - Page 24
is43r32800b
Manufacturer Part Number
is43r32800b
Description
8mx32 256mb Ddr Synchronous Dram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
1.IS43R32800B.pdf
(39 pages)
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IS43R32800B
24
OPERATIONAL DESCRIPTION
BANK ACTIVATE
the bank addresses (BA 0,1). A row is indicated by the row address A0-11. The minimum activation
PRECHARG E
prechargeall command (PRE A, PRE+ A8 =H) is available to deactivate them at the same time. A fter
tRP from the precharge, an AC T c ommand to the same bank can be issued.
interval betweenone bank and the other bank is tRRD .
The DDR SDRAM has four independent banks. E ach bank is activated by the ACT command with
The PRE command deactivates the bank indicated by BA 0,1. When multiple banks are active, the
A0-7 ,9-11
Command
A precharge command can be issued at BL/2 from a read command without data loss.
BA 0,1
/CLK
DQS
CL K
A8
DQ
2 ACT comma nd / tRCmi n
AC T
Xa
Xa
00
Bank Activation and PrechargeAll (BL=8, CL=2)
tRRD
tRCD
AC T
01
Xb
Xb
RE AD
Y
0
00
tRCmin
BL /2
tRAS
Qa0
Qa1
Integrated Silicon Solution, Inc. — www.issi.com
Qa2
Precharge all
Qa3
PR E
1
Qa4
Qa5
tRP
Qa6
Qa7
AC T
Xb
Xb
01
Rev. 00D
03/19/08