is42sm16200c Integrated Silicon Solution, Inc., is42sm16200c Datasheet - Page 18
is42sm16200c
Manufacturer Part Number
is42sm16200c
Description
1m X 16bits X 2banks Low Power Synchronous Dram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
1.IS42SM16200C.pdf
(33 pages)
- Current page: 18 of 33
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Rev. 00A | July 2010
Note :
1. H: Logic High, L: Logic Low, X: Don't care
2. For the given current state CKE must be low in the previous cycle.
3. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
4. The address inputs depend on the command that is issued.
5. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state.
6. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes
high and is maintained for a minimum 100usec
high and is maintained for a minimum 100usec.
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IS42SM/RM/VM16200C
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