nvt2001 NXP Semiconductors, nvt2001 Datasheet - Page 7
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
nvt2001
Manufacturer Part Number
nvt2001
Description
Bidirectional Voltage Level Translator For Open-drain And Push-pull Applications
Manufacturer
NXP Semiconductors
Datasheet
1.NVT2001.pdf
(26 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
nvt2001GM
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
NVT2001_NVT2002
Product data sheet
7.2 Bidirectional translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower
voltage to higher voltage), the EN input must be connected to VREFB and both pins pulled
to HIGH side V
regulate the EN input. A filter capacitor on VREFB is recommended. The master output
driver can be totem pole or open-drain (pull-up resistors may be required) and the slave
device output can be totem pole or open-drain (pull-up resistors are required to pull the Bn
outputs to V
the outputs must be 3-stateable and be controlled by some direction-control mechanism
to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no
direction control is needed.
The reference supply voltage (V
voltage. When VREFB is connected through a 200 kΩ resistor to a 3.3 V to 5.5 V V
power supply, and V
has a maximum output voltage equal to VREFA, and the output of each Bn has a
maximum output voltage equal to V
Fig 10. Bidirectional translation to multiple higher voltage levels
1.8 V
1.5 V
1.2 V
1.0 V
V
CORE
pu(D)
CPU I/O
pu(D)
All information provided in this document is subject to legal disclaimers.
). However, if either output is totem-pole, data must be unidirectional or
through a pull-up resistor (typically 200 kΩ). This allows VREFB to
ref(A)
Rev. 1 — 30 August 2010
is set between 1.0 V and (V
VREFA
ref(A)
A1
A2
A3
A4
A5
A6
An
NVT20XX
pu(D)
SW
SW
SW
SW
SW
SW
SW
GND
) is connected to the processor core power supply
.
B1
B2
B3
B4
B5
B6
Bn
EN
VREFB
NVT2001; NVT2002
200 kΩ
Bidirectional voltage level translator
pu(D)
− 1 V), the output of each An
CHIPSET I/O
CHIPSET I/O
© NXP B.V. 2010. All rights reserved.
V
V
CC
CC
5 V
totem pole or
open-drain I/O
3.3 V
002aae133
pu(D)
7 of 26