tp3155 National Semiconductor Corporation, tp3155 Datasheet - Page 5

• Manufacturer Part Number: tp3155
• Description: Tp3155 Time Slot Assignment Circuit
• Manufacturer: National Semiconductor Corporation

Functional Description
OPERATING MODES
The TP3155 control interface requires an 8-bit serial control
word which is compatible with the TP3020 TP3021 and
2910 2911 CODECs Two bits X and R define which of the
two groups of frame sync outputs FS
FS
ment field specifies the selected time slot from 0 to 31 A
frame sync output is active-high for one time slot which is
always 8 cycles of BCLK A frame may consist of any num-
ber of time slots up to 32 If a timeslot is assigned which is
beyond the number of time slots in a frame the FS
output to which it was assigned will remain inactive
Two modes of operation are available Mode 1 is for sys-
tems requiring different time slot assignments for the trans-
mit and receive direction of each channel Mode 1 is select-
ed by leaving pin 9 (MODE) open-circuit or connecting it to
V
the start of each receive frame and the four outputs
FS
XSYNC input defines the start of each transmit frame and
outputs FS
XSYNC may have any phase relationship with RSYNC In-
puts CH0 and CH1 select the channel from 0 to 3 (see
Table Ia)
Mode 2 provides the option of assigning all 8 frame sync
outputs with respect to the XSYNC input Mode 2 is select-
ed by connecting pin 9 (MODE) to GND This makes the
TP3155 TSAC useful for either an 8-channel undirectional
controller or for systems in which the transmit and receive
directions of each channel are always assigned to the same
time slot as the other i e the FS
COMBO CODEC Filter are hard-wired together In this
case logical selection of the channel to be assigned is
made via inputs CH0 CH1 and CH2 (see Table Ib)
POWER-UP INITIALIZATION
During power-up all frame sync outputs FS
FS
active until a valid time slot assignment is made
LOADING CONTROL DATA
During the loading of control data the binary code for the
selected channel must be set on inputs CH0 and CH1 (and
CH2 in mode 2) see Tables Ia and Ib
Control data is clocked into the D
edges of CLK
A new time slot assignment is transferred to the selected
assignment register on the high going transition of CS The
new assignment is re-synchronized to the system clock
such that the new FS output pulses will start at the next
complete valid time slot after the rising edge of CS
TIME SLOT COUNTER OPERATION
At the start of TS0 of each transmit frame defined by the
first falling edge of BCLK after XSYNC goes high the trans-
mit time slot counter is reset to 000000 and begins to incre-
ment once every 8 cycles of BCLK Each count is compared
with the 4 transmit assignment registers and on finding a
match a frame sync pulse is generated at that FS
Similarly the first falling edge of BCLK after RSYNC goes
high defines the start of receive TS0
FS
receive time slot counter matches the appropriate receive
assignment register
CC
R
R
R
R
3 is affected by the control word and a 6-bit assign-
0 – FS
0 – FS
0 – FS
In this case Pin 13 is the RSYNC input which defines
R
R
R
3 are assigned with respect to RSYNC The
X
3 are inhibited and held low No outputs will go
3 are generated with respect to TS0 when the
0 – FS
C
while CS is low
X
3 are assigned with respect to XSYNC
X
and FS
C
X
0 to FS
input on the falling
R
X
X
inputs on the
and outputs
0 – FS
3 or FS
X
X
X
or FS
output
3 and
R
0 to
R
5
TS
In mode 1 (separate transmit and receive assignments) this
output pulls low whenever any FS
generated In mode 2 this output pulls low whenever any
FS
open-circuit allowing the TS
TSACS to be wire-ANDed together with a common pull-up
resistor This signal can be used to control the TRI-STATE
enable input of a line driver to buffer the transmit PCM bus
from the CODEC Filters to the backplane
X is the first bit clocked into the D
Note 1 When T5
X
0
0
1
1
T5
X
X
0
0
1
1
X
X
0
0
0
0
0
1
CH2
CH1
or FS
OUTPUT
0
0
0
0
1
1
1
1
0
1
1
0
R
0
1
0
1
R
R
0
1
0
1
T4
R
X
0
0
0
1
1
Assign time slot to both selected FS
Assign time slot to selected FS
Assign time slot to selected FS
Disable both selected FS
output is being generated At all other times it is
(TP3020 TP3021 Compatible)
e
CH1
CH0
T5
TABLE Ib Control Mode 2
(
TABLE Ia Control Mode 1
0
0
1
1
0
0
1
1
1 then the appropriate FS
T3
0
1
0
1
X
0
0
0
1
1
Control Data Format
Assign time slot to selected output
Disable selected output
T4
T2
X
0
0
0
1
1
CH0
C
Assign to FS
Assign to FS
Assign to FS
Assign to FS
0
1
0
1
0
1
0
1
input
X
T3
Action
T1
Channel Selected
X
0
0
1
1
1
Action
outputs of a number of
X
X
Channel Selected
output pulse is being
X
and FS
T2
Assign to FS
Assign to FS
Assign to FS
Assign to FS
Assign to FS
Assign to FS
Assign to FS
Assign to FS
or FS
T0
x
x
x
x
0
1
0
0
1
X
0 and or FS
1 and or FS
2 and or FS
3 and or FS
X
R
R
only
only
output is inactive
R
T1
Time Slot
X
(Note 1)
and FS
30
31
0
1
2
X
X
X
X
R
R
R
R
0
1
2
3
R
R
R
R
0
1
2
3
T0
0
1
2
3
R