pef22554e Infineon Technologies Corporation, pef22554e Datasheet - Page 16

• Manufacturer Part Number: pef22554e
• Description: Quad E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

1.11
The register settings for flexible master clock can be calculated as follows. For some
standard frequencies see
located in registers GCM1 to GCM8.
1. PLL_M and PLL_N must fulfill the equations:
a.
for PLL_M = 0 to 31:
b.
for PLL_N = 25 to 63:
for PLL_N = 0 to 24:
Attention: To decrease sensitivity of PLL to noise on V
c.
2. Selection of dividing mode to best fulfill:
Though the target frequency might not be met directly, the dividing mode has to be
selected to reach a frequency which is as near as possible to the target frequency.
Delta Sheet
f
f
outE1
outT1
Flexible Clock Mode Settings
f
pdref
=
=
f
f
MCLK
260 MHz f
MCLK
(as high as possible within this range)
as high as possible.
5.0 MHz
1.0 MHz
f
×
pdref
×
æ
---------------------------------------------------------------------------------------------------- -
è
æ
---------------------------------------------------------------------------------------------------- -
è
PHSN_E1
PHSN_T1
≤
≤
Table 5
≤
=
f
MCLK
f
pdref
pdref
--------------------------- -
PLL_M + 1
f
MCLK
≤
×
≤
+
4
below. The variables used in these calculations are
+
15.0 MHz
4
6.0 MHz
4
---------------------------------------- -
PHSX_E1
------------------------ -
×
PHSX_T1
------------------------ -
×
×
(
PLL_M
(
PLL_N
(
PLL_N
PLL_N
6
16/30
6
ö
ø
+
ö
ø
+
+
×
+
1
×
1
1
(
1
)
(
PLL_M
)
)
PLL_M
≤
395.26 MHz
+
+
1
1
)
DDP
)
≅
≅
2 16.384 MHz
2 12.352 MHz
×
and/or V
×
QuadFALC
PEF 22554
SSP
2002-09-16
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