cp2120 Silicon Laboratories, cp2120 Datasheet - Page 9

• Manufacturer Part Number: cp2120
• Description: Single Chip Spi To I2c Transfer Integrated Clock; No External Clock Required On-chip Voltage Monitor
• Manufacturer: Silicon Laboratories

5. SPI Slave Bus
The CP2120 provides a four-wire slave SPI interface. The CP2120's SPI Bus activates whenever the SPI Master
pulls the NSS pin low. The master can then clock data into the CP2120 through the Master-Out-Slave-In (MOSI)
pin and receive data from the CP2120 through the Master-In-Slave-Out (MISO) pin. The SPI Master provides the
SPI with a clock source. Figure 2 shows typical connections for an SPI bus.
SCLK should be held high when idle. Figure 3 shows a CP2120 data transfer on the SPI Bus. If the CP2120 is the
only slave device on the SPI bus, the NSS pin can be tied low.
SCK
MOSI
MISO
NSS
MSB
MSB
SPI Master
Bit 6
Bit 6
SPICLK
Figure 3. Slave Mode Data/Clock Timing
Figure 2. SPI Bus Typical Connections
CS
Bit 5
Bit 5
MISO
MOSI
SCLK
CS
Rev. 0.3
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
CP2120
Bit 1
Bit 1
Bit 0
CP2120
Bit 0
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