lu82562ex Intel Corporation, lu82562ex Datasheet - Page 21
lu82562ex
Manufacturer Part Number
lu82562ex
Description
Dual Footprint
Manufacturer
Intel Corporation
Datasheet
1.LU82562EX.pdf
(66 pages)
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3.2.2
Figure 5. LAN Disable Circuitry
Note: The 100 Ω resistors for the Test Mode signals are required for the Exclusive OR (XOR) Tree and
Serial EEPROM for 82562EZ(EX) Implementations
Isolate Mode.
Serial EEPROM for LAN implementations based on 82562EZ(EX) devices connects to the ICH5.
Depending upon the size of the EEPROM, the 82562EZ(EX) may or may not support legacy
manageability.
details on the EEPROM, refer to the appropriate I/O Control Hub 2, 3, 4, 5, 6, and 7 EEPROM
Map and Programming Information.
NOTE: No manageability provided.
Table 7.
24, 25, 27, 28
µController
ICHx GPIO
Super IO
(mobile)
GP Port
or
or
Supervisor
Table 7
Sensor/
82562EZ(EX) Memory Layout (128 Byte EEPROM)
00h
3Fh
3.3Vstb
HW/SW Reserved Area
and
RST#
1K
3.3Vstb
Table 8
list the EEPROM map for the 82562EZ(EX) PLC device. For
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
1K
MMBT3904
LAN_RST#
RSMRST#
3.3Vstb
470 Ω
ICHx
100 Ω
100 Ω
100 Ω
100 Ω
TESTEN
ISOL_TCK
ISOL_TI
ISOL_TEX
13
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