peb20954 Infineon Technologies Corporation, peb20954 Datasheet - Page 54
peb20954
Manufacturer Part Number
peb20954
Description
Smart Integrated Digital Echo Canceller Sidec
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB20954.pdf
(132 pages)
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PEB 20954
PEF 20954
Operational Description
4.3.8
Microprocessor Interface
The SIDEC Microprocessor Interface supports both, SIEMENS/Intel and Motorola mode.
In each mode the address can be provided either through the multiplexed address/data
or a parallel address bus. In multiplexed mode the address is always sampled with the
falling edge of the address latch enable signal on the lower 7 bits of the multiplexed
address/data bus. hence, adresses from 00H to 7FH are possible.
Read and write access in Intel mode is controlled by the assigned read and write signals.
In Motorola mode it is provided by the data strobe and read/write signal.
The chip select signal is internally simply ’ored’ with the read and write signal in Intel
mode and with the data strobe signal in Motorola mode, thus enabling register access
through chip select controlled Microprocessor cycles.
For fast processors there is also a ready/acknowledgment signal provided in order to
eliminate the need for processor configured wait state insertion.
To write a value in a write protected register the value 95H needs to be written in the
register Write Protection.
Preliminary Data Sheet
54
04.99
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