peb20954 Infineon Technologies Corporation, peb20954 Datasheet - Page 100

• Manufacturer Part Number: peb20954
• Description: Smart Integrated Digital Echo Canceller Sidec
• Manufacturer: Infineon Technologies Corporation

Preliminary Data Sheet
STFALL[2:0]
AMPL[1:0]
AFSTC[6:4,2:0] (Addr.:71H): AFI Filter Spring Timer Configuration, write protected,
Reset value = 44H
Additional damping of the Coefficients. This feature is disabled as soon as the
coefficients are frozen.
ACSPT[2:0]
CSPT[2:0]
AEEPD[3:0] (Addr.: 72H): AFI End Echo Path Delay, write protected, Reset value = 0FH
DELAY[3:0]
-
-
SPT[2]
AC
-
,
Saw-tooth falling clock frequency
The clock for the increasing a decreasing saw tooth offset voltage
is:
"000": 4 kHz
"010": 1 kHz
"100": 250 Hz
"110": 62.5 Hz
If STRISE[2:0] and STFALL[2:0] are set to "000", the clock will be
switched off.
Saw-tooth and offset amplitude:
The maximum values of the saw tooth characteristic or offset (clock
is switched off) are:
"00": 15
"10": 63
These values will be added to the linearized receive path signals.
The max. linearized value in A/ Law Code is 8064/8031
Aux. coefficients spring timer
Coefficients spring timer
The period for ACSPT[2:0] and CSPT[2:0] is:
"000": 250 s
"010": 1 ms
"100": 4ms
"110": 16 ms
End echo path delay:
Depending on the presumed delay in the end echo path, this register
is set to DELAY := <echo_delay> / 8 ms -1. Thus, the AFI handles
end echo path delays in the range 8 ms to 128 ms. For end echo
SPT[1]
AC
-
SPT[0]
AC
-
100
"001": 2 kHz
"011": 500 Hz
"101": 125 Hz
"111": 31.25 Hz
"01": 31
"11": 127
"001": 500 s
"011": 2 ms
"101": 8 ms
"111": 32 ms
DELAY
[3]
-
DELAY
SPT[2]
[2]
C
Register Description
DELAY
SPT[1]
[1]
C
PEB 20954
PEF 20954
DELAY
SPT[0]
[0]
C
04.99